What Comes After FinFETs?

FinFETS can scale to 5nm, and after that there are a slew of possibilities; determining factors will be cost and manufacturability.

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By Mark LaPedus
The semiconductor industry is currently making a major transition from conventional planar transistors to finFETs starting at 22nm.

The question is what’s next? In the lab, IBM, Intel and others have demonstrated the ability to scale finFETs down to 5nm or so. If or when finFETs runs out of steam, there are no less than 18 different next-generation candidates that could one day replace today’s CMOS-based finFET transistors.

But even the large companies with deep pockets don’t have the time or resources to work on all technologies. “We can’t pick 18,” said Mike Mayberry, vice president and director of components research in the Technology and Manufacturing Group at Intel Corp. “We will develop only a few of them.”

Mayberry said the eventual winners and losers in the next-generation transistor race will be determined by cost, manufacturability and functionality. “The best device is the one you can manufacture,” he said.

In fact, the IC industry is already weeding out the candidates. In 2005, the Semiconductor Research Corp. (SRC), a chip R&D consortium, launched the Nanoelectronics Research Initiative (NRI), a group that is researching futuristic devices capable of replacing the CMOS transistor in the 2020 timeframe. NRI member companies include GlobalFoundries, IBM, Intel, Micron and TI.

So far, the NRI has narrowed down and identified a handful of serious contenders: gate-all-around, silicon nanowires, tunnel field-effect transistors (TFETs), carbon nanotubes, graphene devices, and bilayer pseudo-spin field-effect transistors (BiSFETs).

It’s still too early to determine which future transistor candidate will prevail, said Steven Hillenius, executive vice president of the SRC. “There is still no consensus,” Hillenius said, “but we’ve gone from 20 or so potential devices down to less than 10.”

The finFET and beyond
For now, the industry is banking on the finFET transistor to enable IC scaling for the foreseeable future. The current thinking is that today’s finFET will likely scale at least two generations down to 10nm, said Subramani Kengeri, head of advanced technology architecture at GlobalFoundries. Then, at 7nm, the industry is looking at next-generation finFETs based on III-V or other materials to provide a mobility boost, Kengeri said. It’s too early to predict a winner, as “nothing has been settled,” he added.

Indeed, the future is cloudy at and beyond 10nm. According to the 2011 ITRS roadmap, there are a dizzying array of next-generation transistor options on the table: III-V channel replacement finFETs, carbon nanotube FETs, graphene nanoribbon FETs, nanowire FETs, tunnel FETs, spin FETs, IMOS, negative gate capacitance FETs, NEMS switches, atomic switches, MOTT FETs, spin wave devices, nanomagnetic logic, excitonic FETs, BiSFETs, spin torque majority logic gate and all spin logic.

The futuristic candidates likely will require new materials, manufacturing flows and design methodologies. At the SRC, there is one basic criterion to help narrow down the playing field: “The promising new structures are the ones you can put in the current manufacturing flow. The new materials would be used in conjunction with what we are using now,” said SRC’s Hillenius.

For that reason, one transistor candidate has emerged as the favorite in the race. “At this point, the tunnel FET looks like the best option,” said Chenming Calvin Hu, professor of microelectronics at the University of California at Berkeley. Using III-V materials for the channels, TFETs potentially could extend CMOS. Claiming eight times the performance of today’s MOSFETs, TFETs enable a steeper sub-threshold slope less than 60 mV/decade. In TFET, a tunnel barrier is created at the source- channel contact in order to increase the drive current of the transistor.

“It’s likely that the industry will stay with finFETs or tri-gates for the 22nm and 14nm nodes. The earliest introduction of III-V MOSFETs is likely is at the 10nm node. This implies that III-V TFETs will appear no sooner than the 7nm technology node,” said Suman Datta, professor of electrical engineering at Pennsylvania State University.

In the lab, Intel has shown TFETs based on III-V materials like InGaAs. “Penn St. and Notre Dame have been able to use staggered and broken gap tunnel junctions in In(Ga)As/Ga(As)Sb TFETs to demonstrate competitive on-current in experimental devices. These TFETs have all been n-channel demonstrations. Very little work has been toward p-channel TFETs and the next challenge would be the demonstration of steep switching p-channel TFET for complementary TFET logic,” Datta said.

“The biggest barrier is the introduction of III-V compound semiconductors within a state-of-the-art silicon fab. III-V islands need to be grown selectively on 300mm, or by that time on 450mm substrates, with low defect count using a high volume manufacturing technique,” Datta said.

Besides TFETs, silicon nanowires also could be classified as “an extension to the finFET,’’ said Gary Patton, vice president of the Semiconductor Research and Development Center at IBM. Silicon nanowire field-effect transistors (FETs) are structures in which the conventional channel is replaced with tiny nanowires.

Nanowires also enable what’s considered to be the ultimate solution in the IC industry: gate-all-around (GAA) finFETs. GAA FETs can have two or more gates, which are wrapped around by a nanowire channel. In a recent paper, Harvard University and Purdue University demonstrated a gate-all-around III-V MOSFET. The device itself boasts 1, 4, 9 or 19 nanowire channels. One of the key fabrication steps is a controlled release process, which is used to form the InGaAs nanowire channels.

“We would likely see GAA devices two to three generations after tri-gate/finFET technology,” said Jiangjiang Gu, a Ph.D. candidate at the Department of Electrical and Computer Engineering at Purdue. “The biggest challenge for GAA devices with III-V channels is how to fabricate ultra-small nanowires with high mobility surfaces and low interface trap densities by a top-down technology. Other challenges include how to form low resistance contacts to these nanowires and how to reduce variations of the GAA devices.”

Carbon nanotubes and graphene
TFETs, nanowire FETs and GAA are arguably the most straightforward extensions to CMOS. Two other options, carbon nanotubes and graphene-based devices, are promising but more exotic approaches. Carbon nanotubes are grown on full wafers and aligned in one direction. They are subsequently transferred to a target substrate multiple times. IBM, for one, has demonstrated sub-10nm carbon nanotubes.

Carbon nanotube FETs (CNFETs) are “the only FET that is projected to outperform the 11nm node ITRS target,” said H. S. Philip Wong, professor of electrical engineering at Stanford University, in a recent paper. CNFETs, according to Wong, face three major challenges: aligned density; stable p- and n-type doping on the same wafer; and low resistance metal to contact at short contact lengths.

In contrast, graphene consists of one-atom-thick planar sheets, which are packed in honeycomb crystal lattice structures. The technology is expensive and difficult to put into manufacturing. And it doesn’t have a band gap, meaning it can’t be turned off in a system.

Still, there is interest in using graphene as a channel replacement material. IBM, for one, is looking at analog and RF applications for graphene FETs (GFETs). The company has demonstrated a GFET running at 155-GHz with 40nm channel lengths.

In another approach, the University of Texas at Austin has been developing the BiSFET, which is said to have 1,000 times lower power consumption than CMOS. In this device, a p- and an n-type layer of graphene are separated by a dielectric tunnel barrier. Each graphene layer has a metallic contact and is electrostatically coupled to a gate electrode.

“The device is still in an R&D phase. While we have theoretically shown that it should work, we are still struggling to demonstrate functionality in the lab. So at this point, it is premature to think of large scale production,” said Sanjay Banerjee, professor of electrical and computer engineering and director of the Microelectronics Research Center at the University of Texas at Austin.

Researchers are also looking at other technologies. For example, all spin logic (ASL) is gaining interest. ASL uses magnets to represent non-volatile binary data, while the communication between magnets is achieved using spin currents.

Despite the promising research for spin logic and other futuristic devices, the industry faces many challenges to find the right candidate. “Predicting what lies ahead is fraught with peril as our ability to see is dependent on where and how we look,” Intel’s Mayberry said.