tag: finFETs

Increasing Levels Of Risk
By Ed Sperling - 13 Dec, 2012 - Comments: 0

Semiconductor Manufacturing & Design sits down with Mentor Graphics' Jean-Marie Brunet to talk about double patterning, finFETs, design rules at advanced nodes and why design for manufacturing (DFM) has suddenly become so popular. [youtube vid=3GHvikyjZow] » read more

Upping The Ante
By Ed Sperling - 13 Dec, 2012 - Comments: 0

The increasing number of research projects under way to solve many of the thorniest issues in the history of semiconductor design and manufacturing are a testament to just how tough the job has become. Never before have there been so many technological roadblocks at the same time—and so many potential options for solving them. Those challenges—or opportunities, as marketing execs like to... » read more

Remaking The Playing Field
By Ed Sperling - 30 Nov, 2012 - Comments: 0

Just a week ago the battle lines looked very well defined. ARM was fighting Intel on power, and Intel was fighting ARM on performance. One week later, ARM has cemented a deal with AMD, which will use its cores in future processors running Microsoft software. Imagination Technologies is buying MIPS, which presumably it will use to go after both ARM and Intel. And Intel has a stake in Imaginat... » read more

Node Skipping Reaches New Heights
By Ed Sperling - 15 Nov, 2012 - Comments: 0

By Mark LaPedus For years, silicon foundries have rolled out their respective leading-edge processes roughly on a two-year cadence. The long-standing goal has been to keep foundry customers on a competitive price, power and performance curve. But as leading-edge chipmakers move from the 28nm node and beyond, the predictable process progression is changing. And the phenomenon of “node skip... » read more

Experts At The Table: Obstacles In Low-Power Design
By Ed Sperling - 08 Nov, 2012 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss low-power design with with Leah Clark, associate technical director at Broadcom; Richard Trihy, director of design enablement at GlobalFoundries; Venki Venkatesh, engineering director at Atrenta; and Qi Wang, technical marketing group director at Cadence. What follows are excerpts of that conversation. LPHP: What are ... » read more

Innovative Wafers For Energy-Efficient CMOS Technology
By Various Writers - 18 Oct, 2012 - Comments: 0

For continued attractiveness and competitiveness of advanced electronic appliances such as smartphones, TVs, notebooks or tablets, the semiconductor industry is moving to “fully depleted” transistor technology to build integrated circuits. This technology comes in two flavors: planar and tri-dimensional (FinFET), each with its own advantages and challenges. This White Paper explains how inn... » read more

New Math
By Ed Sperling - 18 Oct, 2012 - Comments: 0

It was nice when we had round numbers to work with. It was pretty simple to move from 180nm to 120nm and then to 90nm. Then the half nodes started—45/40, 32/28 and 22/20nm. After 14nm we are poised dangerously over the single-digit process nodes. Intel is working on 10nm, to be followed by 7nm or 5nm. Other companies are looking at 11nm, to be followed by 8nm, 6nm or something even further... » read more

Experts At The Table: IC Manufacturing Challenges
By Ed Sperling - 01 Oct, 2012 - Comments: 0

By Mark LaPedus Semiconductor Manufacturing & Design sat down with Carlos Mazure, chief technical officer at Soitec; Jeff Hebb, vice president of laser product marketing at Ultratech; Markus Wimplinger, corporate technology development and IP director at EV Group; and Girish Dixit, vice president of the customer integration center and process interactions at Lam Research. What follows are ... » read more

Near-Threshold Computing
By Bhanu Kapoor - 13 Sep, 2012 - Comments: 0

By Bhanu Kapoor There were two main contributing factors to power becoming a big problem ("The Power Wall") starting around the 65nm process technology. First, the fast-growing leakage component became as significant as the dynamic power. Second, the scaling of the supply voltage stopped around 1.1 volts. Process technology advances such as HKMG and 3D tri-gate transistors have enabled con... » read more

The Trouble With FinFETs
By Joanne Itow - 16 Aug, 2012 - Comments: 0

By Joanne Itow The industry’s quest to continue on the semiconductor roadmap defined by Moore’s Law has led to the adoption of a new transistor structure. Whether you call them finFETs, tri-gate or 3D transistors, building these new devices is difficult. But the technology is only half the challenge. In 2002, Chen Ming Hu* spoke at the Semico Summit. The title of his presentation was �... » read more

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