tag: formal verification

How To Optimize Verification
By Brian Bailey - 25 Jul, 2019 - Comments: 0

The rate of improvement in verification tools and methodologies has been nothing short of staggering, but that has created new kinds of problems for verification teams. Over the past 20 years, verification has transformed from a single language (Verilog) and tool (simulator) to utilizing many languages (testbench languages, assertion languages, coverage languages, constraint languages), many... » read more

Complete Formal Verification of RISC V Processor IPs for Trojan-Free Trusted ICs
By OneSpin Solutions - 26 Jun, 2019 - Comments: 0

RISC-V processor IPs are increasingly being integrated into system-on-chip designs for a variety of applications. However, there is still a lack of dedicated functional verification solutions supporting high-integrity, trusted integrated circuits. This paper examines an efficient, novel, formal-based RISC-V processor verification methodology. The RISC-V ISA is formalized in a set of Operational... » read more

Who’s Responsible For Security Breaches?
By Brian Bailey - 24 Jun, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss industry attitudes towards safety and security with Dave Kelf, chief marketing officer for Breker Verification; Jacob Wiltgen, solutions architect for functional safety at Mentor, a Siemens Business; David Landoll, solutions architect for OneSpin Solutions; Dennis Ciplickas, vice president of characterization solutions at PDF Solutions; Andrew Dauma... » read more

How To Integrate An Embedded FPGA
By Brian Bailey - 30 May, 2019 - Comments: 1

Choosing to add programmable logic into an SoC with an eFPGA is just the beginning. Other choices follow involving how many lookup tables (LUTs), how much routing and what topology, how will data be transferred in and out of the fabric, does data need to be coherent with system memory, how will it be programmed and tested, and what RTL functions need to be embedded into the programmable fabric ... » read more

Adding Order And Structure To Verification
By Brian Bailey - 30 May, 2019 - Comments: 0

You can't improve what you can't measure, and when it comes to methodologies the notion of measurement becomes more difficult. Add in notions of the skills, capabilities and experience levels of individuals within an organization, which may affect their ability to adopt certain technologies, and it requires considerable attention. This is where concepts such as capability maturity models (CM... » read more

Evolution Of Verification Engineers
By Brian Bailey - 22 May, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss the implications of having an executable specification that drives verification with Hagai Arbel, chief executive officer for VTool; Adnan Hamid, chief executive office for Breker Verification; Mark Olen, product marketing manager for Mentor, a Siemens Business; Jim Hogan, managing partner of Vista Ventures; Sharon Rosenberg, senior solutions archit... » read more

Billion-Gate Design Connectivity
By Ed Sperling - 27 Mar, 2019 - Comments: 0

Sasa Stamenkovic, senior field application engineer at OneSpin Solutions, explains how to find and resolve connectivity issues in integrating large numbers of components in very big designs, often at the leading edge nodes and in markets such as AI. » read more

Formal Apps Take The Bias Out Off Functional Verification
By Mentor, a Siemens Business - 27 Mar, 2019 - Comments: 0

The Questa Formal Apps automate common formal analysis tasks, providing a multiple set of tools for formal verification experts and novices alike. Each of these automated tasks are integrated into a holistic, formal analysis workflow that allows you to use what you need when you need it. This paper describes common verification challenges and how specific Questa Formal Apps handle them along wi... » read more

The Challenge Of RISC-V Compliance
By Brian Bailey - 28 Feb, 2019 - Comments: 0

The open-source RISC-V instruction set architecture (ISA) continues to gain momentum, but the flexibility of RISC-V creates a problem—how do you know if a RISC-V implementation fits basic standards and can play well with other implementations so they all can run the same ecosystem? In addition, how do you ensure that ecosystem development works for all implementations and that all cores that ... » read more

Building Security Into RISC-V Systems
By Ed Sperling - 30 Jan, 2019 - Comments: 0

Semiconductor Engineering sat down with Helena Handschuh, a Rambus fellow; Richard Newell, senior principal product architect at Microsemi, a Microchip Company; and Joseph Kiniry, principal scientist at Galois. Part one is here. (This is the second of two parts.) L-R: Joseph Kiniry, Helena Handschuh, Richard Newell. SE: Some of the new applications for hardware designs are tied to AI, d... » read more

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