tag: formal verification

How To Integrate An Embedded FPGA
By Brian Bailey - 30 May, 2019 - Comments: 1

Choosing to add programmable logic into an SoC with an eFPGA is just the beginning. Other choices follow involving how many lookup tables (LUTs), how much routing and what topology, how will data be transferred in and out of the fabric, does data need to be coherent with system memory, how will it be programmed and tested, and what RTL functions need to be embedded into the programmable fabric ... » read more

Adding Order And Structure To Verification
By Brian Bailey - 30 May, 2019 - Comments: 0

You can't improve what you can't measure, and when it comes to methodologies the notion of measurement becomes more difficult. Add in notions of the skills, capabilities and experience levels of individuals within an organization, which may affect their ability to adopt certain technologies, and it requires considerable attention. This is where concepts such as capability maturity models (CM... » read more

Evolution Of Verification Engineers
By Brian Bailey - 22 May, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss the implications of having an executable specification that drives verification with Hagai Arbel, chief executive officer for VTool; Adnan Hamid, chief executive office for Breker Verification; Mark Olen, product marketing manager for Mentor, a Siemens Business; Jim Hogan, managing partner of Vista Ventures; Sharon Rosenberg, senior solutions archit... » read more

Billion-Gate Design Connectivity
By Ed Sperling - 27 Mar, 2019 - Comments: 0

Sasa Stamenkovic, senior field application engineer at OneSpin Solutions, explains how to find and resolve connectivity issues in integrating large numbers of components in very big designs, often at the leading edge nodes and in markets such as AI. » read more

Formal Apps Take The Bias Out Off Functional Verification
By Mentor, a Siemens Business - 27 Mar, 2019 - Comments: 0

The Questa Formal Apps automate common formal analysis tasks, providing a multiple set of tools for formal verification experts and novices alike. Each of these automated tasks are integrated into a holistic, formal analysis workflow that allows you to use what you need when you need it. This paper describes common verification challenges and how specific Questa Formal Apps handle them along wi... » read more

The Challenge Of RISC-V Compliance
By Brian Bailey - 28 Feb, 2019 - Comments: 0

The open-source RISC-V instruction set architecture (ISA) continues to gain momentum, but the flexibility of RISC-V creates a problem—how do you know if a RISC-V implementation fits basic standards and can play well with other implementations so they all can run the same ecosystem? In addition, how do you ensure that ecosystem development works for all implementations and that all cores that ... » read more

Building Security Into RISC-V Systems
By Ed Sperling - 30 Jan, 2019 - Comments: 0

Semiconductor Engineering sat down with Helena Handschuh, a Rambus fellow; Richard Newell, senior principal product architect at Microsemi, a Microchip Company; and Joseph Kiniry, principal scientist at Galois. Part one is here. (This is the second of two parts.) L-R: Joseph Kiniry, Helena Handschuh, Richard Newell. SE: Some of the new applications for hardware designs are tied to AI, d... » read more

What Makes A Chip Design Successful Today?
By Brian Bailey - 13 Dec, 2018 - Comments: 0

"Transistors are free" was the rallying cry of the semiconductor industry during the 1990s and early 2000s. That is no longer true. The end of Dennard scaling made the simultaneous use of all the transistors troublesome, but transistors remained effectively unlimited. This led to an era where large amounts of flexibility could be built into a chip. It didn't matter if all of it was being use... » read more

Autonomous Vehicle Design Begins To Change Direction
By Ann Mutschler - 06 Dec, 2018 - Comments: 0

Tools that are commonly used in semiconductor design are starting to be applied at the system level for assisted and autonomous vehicles, setting the stage for more complex simulated scenarios and electronic system design. Simulation is well understood for designing automotive ICs, but now it also is being used to design vehicle architectures and sensors, as well as for sensor miniaturizatio... » read more

Mitigating Risk Through Verification
By Ann Mutschler - 05 Dec, 2018 - Comments: 0

Verification is all about mitigating risk, and one of the growing issues alongside of increasing complexity and new architectures is coverage. The whole notion of coverage is making sure a chip will work as designed. That requires determining the effectiveness of the simulation tests that stimulate it, and its effectiveness in terms of activating structures of functional behavior and design.... » read more

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