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Addressing The Challenges Of Reset Verification In SoC Designs

How to build a complete solution with static analysis of the design, RTL simulation with X-propagation, and formal verification.

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This paper presents commonly occurring challenges involved in reset tree verification and their solutions. We lay out a three part approach to build a complete solution that combines static analysis of the design structure, RTL simulation with X-propagation, and formal verification. The paper includes results from testing this solution on a customer design.

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