tag: formal verification

Blog Review: April 9
By Ed Sperling - 09 Apr, 2014 - Comments: 0

Mentor’s Colin Walls discovered an interesting video of the software programming learning process—a teacher responding literally to commands from his students on how to make a jam sandwich. It’s harder than it looks. Cadence’s Brian Fuller captures a speech by his colleague, Sanjiv Taneja, about the need for a comprehensive verification approach and smart IP reuse. The overriding th... » read more

Post-Silicon Validation Using Formal Analysis
By Various Writers - 09 Apr, 2014 - Comments: 0

Verifying the current generation of complex SoCs requires the best methodology and tools, including the application of high-capacity formal verification technologies throughout the design flow, from architectural exploration to post-silicon debug. We see this last area, post-silicon debug, as an important value delivered by formal technology for design and verification teams who have not employ... » read more

Tech Talk: Debugging IP
By Ed Sperling - 03 Apr, 2014 - Comments: 0

Just because IP is standard doesn't mean it will function as expected in a complex SoC. Ravindra Aneja, senior technical marketing manager at Atrenta, looks at what needs to be done to make sure everything works together. [youtube vid=wlDabbrF2zU] » read more

Formal Is Set To Overtake Simulation
By Brian Bailey - 27 Mar, 2014 - Comments: 4

There has been a significant psychology change in the area of formal verification over the past couple of years. It’s no longer considered a fringe technology, and it’s no longer considered difficult to use. In fact, it has become a necessary part of the verification process. Semiconductor Engineering sat down with a panel of experts to find out what caused this change and what more we c... » read more

Using Formal Verification Across A Spectrum Of Design Applications
By Various Writers - 12 Mar, 2014 - Comments: 0

Chip designers worldwide have told us that Jasper is fundamentally different in how we approach their technical and business problems by delivering a high ROI (return on investment) through the application of advanced formal verification techniques. Our tools address a spectrum of key verification challenges - from getting the architecture unambiguously right, to putting more power in the hands... » read more

The Road Ahead For 2014: Tools
By Brian Bailey - 30 Jan, 2014 - Comments: 0

In the third and final part of this predictions series we see the natural conclusion of market shifts that are driving changes in semiconductors, and which in turn drive the tools and IP needed to create those systems. To be expected, the changes fall into a few areas: New tools, techniques and changes required for smaller geometries; A migration to higher-levels of abstraction and the... » read more

Verifying Security Aspects of SoC Designs with Jasper App
By Various Writers - 15 Jan, 2014 - Comments: 0

This paper presents Jasper technology and methodology to verify the robustness of secure data access and the absence of functional paths touching secure areas of a design. Recently, we have seen an increasing demand in industrial hardware design to verify security information. Complex system-on-chips, such as those for cell phones, game consoles, and servers contain secure information. And it i... » read more

Tech Talk: Security Risks In An SoC
By Ed Sperling - 02 Dec, 2013 - Comments: 1

Lawrence Loh, vice president of engineering at Jasper Design Automation, maps out the security threats in complex systems on chip. [youtube vid=5GBYOnCBfEE] » read more

Do Students Need More Formal Education?
By Brian Bailey - 21 Nov, 2013 - Comments: 0

A few weeks ago, some of the top researchers and practitioners in the area of formal methods converged on Portland, Oregon. The event was the annual Formal Methods in Computer-Aided Design (FMCAD) conference and Semiconductor Engineering attended the panel titled “Teaching Formal Methods: Needs, Challenges, Experiences, and Opportunities.” Panelists included: Jason Baumgartner, formal verif... » read more

Cracking The Tough Nut Using Formal Methods
By Brian Bailey - 21 Nov, 2013 - Comments: 1

Pranav Ashar, CTO of Real Intent, assured a packed room of researchers and practitioners of formal methods at the recent FMCAD conference: “Static verification is being used in the verification of designs. Every major chip out there is using static methods for sign-off today.” He used an analogy of cracking a nut. “There’s a right way and a wrong way and if you don’t pick the right me... » read more

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