tag: formal verification

Rethinking Your Approach To Radiation Mitigation
By Mentor, a Siemens Business - 03 Jun, 2020 - Comments: 0

Formal verification and automation provide an effective, high quality, and repeatable process for fault analysis, protection, and verification for FPGA designs used in high radiation environments. This paper describes an automated systematic approach based on formal verification structural and static analysis that identifies design susceptibility to radiation induced faults. To read more, clic... » read more

Inevitable Bugs
By Brian Bailey - 29 Apr, 2020 - Comments: 3

Are bug escapes inevitable? That was the fundamental question that Oski Technology recently put to a group of industry experts. The participants are primarily simulation experts who, in many cases, help direct the verification directions for some of the largest systems companies. In order to promote free discussion, all comments have been anonymized, distilling the primary thoughts of the parti... » read more

Do You Trust Your IP Supplier?
By Brian Bailey - 26 Mar, 2020 - Comments: 0

How much do you trust your IP supplier, regardless of whether IP was developed in-house or by a third-party provider? And what implications does it have a system integrator? These are important questions that many companies are beginning to ask. Today, there are few methods, other than documentation, that provide the necessary information. The software industry may be ahead of the hardware i... » read more

Speeding Up Verification Using SystemC
By Ed Sperling - 23 Mar, 2020 - Comments: 0

Brett Cline, senior vice president at OneSpin Solutions, explains how adding formal verification into the high-level synthesis flow can reduce the time spent in optimization and debug by about two-thirds, why this needs to be done well ahead of RTL, starting with issues such as initialization, memory out of bounds and other issues that are difficult to find in simulation. » read more

Speeding Up FPGA Development
By Ed Sperling - 28 Feb, 2020 - Comments: 0

Salaheddin Hetalani, field application engineer at OneSpin Solutions, talks about why it’s getting harder to design and debug FPGAs, how much design time can be saved through formal techniques, and why just relying on programmability isn’t the most efficient approach. » read more

Reducing Power At RTL
By Ann Mutschler - 13 Feb, 2020 - Comments: 0

Power management and reduction at the register transfer level is becoming more problematic as more heterogeneous elements are added into advanced designs and more components are dependent on interactions with other components. This has been a growing problem in leading-edge designs for the past couple of process nodes, but similar issues have begun creeping into less-sophisticated designs as... » read more

Ensuring Coverage In Large SoCs
By Ed Sperling - 04 Feb, 2020 - Comments: 0

Sven Beyer, product manager for design verification at OneSpin Solutions, talks about why formal technology is required to ensure coverage in some of the newest chips, how it deals with potential interactions and different use cases, and why it is gaining traction in automotive applications. » read more

Design For Airborne Electronics
By Ann Mutschler - 03 Feb, 2020 - Comments: 0

The Next Generation Air Transportation System (NextGen), an FAA-led modernization of America's air transportation system meant to make flying more efficient, predictable and safer, is currently underway as one of the most ambitious infrastructure projects in U.S. history. This is not just a minor upgrade to an aging infrastructure. The FAA and partners are in the process of implementing new ... » read more

Making Sure RISC-V Designs Work As Expected
By Ann Mutschler - 30 Jan, 2020 - Comments: 0

The RISC-V instruction set architecture is attracting attention across a wide swath of markets, but making sure devices based on the RISC-V ISA work as expected is proving as hard, if not harder, than other commercially available ISA-based chips. The general consensus is that open source lacks the safety net of commercially available IP and tools. Characterization tends to be generalized, ra... » read more

Big Design, IP and End Market Shifts In 2020
By Brian Bailey - 30 Jan, 2020 - Comments: 0

EDA is on a roll. Design starts are up significantly thanks to increased investment in areas such as AI, a plethora of new communications standards, buildout of the Cloud, the race toward autonomous driving and continued advancements in mobile phones. Many designs demand the latest technologies and push the limits of complexity. Low power is becoming more than just reducing wasted power at t... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2024 SMG   |  Terms of Service  |  Privacy Policy