tag: FPGA

Accelerate SoC Simulation Time Of Newer Generation FPGAs
By Aldec - 29 Jul, 2015 - Comments: 0

Comprehensive verification that can be provided by HDL simulators is good, but not ideal. What is necessary is a faster, safer, and more thorough verification environment that combines the robustness of an HDL simulator with the speed of FPGA prototyping boards. The goal is to put together the power of these two verification methodologies into one platform. To read more, click here. » read more

The Week In Review: Manufacturing
By Mark LaPedus - 05 Jun, 2015 - Comments: 1

In what was called a defensive measure by some, Intel has announced a definitive agreement to acquire Altera for $54 per share in an all-cash transaction valued at approximately $16.7 billion. Here’s what one analyst said about the deal. “We continue to believe Intel’s pursuit of Altera–at a significant premium–was based on a defensive position, rather than the purely accretive str... » read more

Blog Review: May 27
By Jesse Allen - 27 May, 2015 - Comments: 0

With the launch of UNICEF and ARM's 'Wearables for Good' design challenge, David Maidment digs into the program's details and how unobtrusive wearables and sensor technology benefits not only consumers in affluent countries, but could improve conditions for those in the developing world as well. From an ultracompact beamsplitter that could boost processing power for supercomputers within the... » read more

Ecosystem Changes
By Ed Sperling - 07 Apr, 2015 - Comments: 0

Semiconductor Engineering sat down to discuss changes in the semiconductor ecosystem with Kelvin Low, senior director of foundry marketing at [getentity id="22865" e_name="Samsung Semiconductor"]; John Costello, vice president of product planning at [getentity id="22849" e_name="Altera"]; Randy Smith, vice president of marketing at [getentity id="22605" e_name="Sonics"], and Michiel Ligthart, p... » read more

Incremental Design Methodologies
By Brian Bailey - 26 Feb, 2015 - Comments: 0

There are times when we become stuck in the past, or choose to believe something that is no longer true or actually never was true. As we get older, we are all guilty of that. History tends to rewrite itself, especially given that this industry is aging. One of these situations occurred recently, and comments from an industry luminary didn’t align with the thoughts and memories of other peopl... » read more

With Responsibility Comes Power
By Brian Bailey - 12 Feb, 2015 - Comments: 0

The debate continues as to whether [getkc id="106" kc_name="power"] has risen to become a primary design consideration, or if it remains secondary to functionality and performance. What is indisputable is the rise in the importance of both power and energy conservation. As technology improves, additional aspects of the design flow are being affected. With that, the focus for power reduction is ... » read more

An Architectural Choice Overdue For Change
By Brian Bailey - 04 Dec, 2014 - Comments: 0

The past appears to be a lot simpler than the present and when we look into the future, the right decisions often look highly uncertain. This is the value of hindsight, but also includes the notion that the winner gets to write history. What semiconductors look like today could have been very different if different decisions had been made 20 years ago. What if the industry had adopted a paralle... » read more

More Than Moore
By Ed Sperling - 15 Sep, 2014 - Comments: 0

Semiconductor Engineering sat down to discuss the value of feature shrinks and what comes next with Steve Eplett, design technology and automation manager at [getentity id="22664" e_name="Open-Silicon"]; Patrick Soheili, vice president and general manager of IP Solutions at [getentity id="22242" e_name="eSilicon"]; Brandon Wang, engineering group director at [getentity id="22032" e_name="Cadenc... » read more

The Week In Review: Design
By Ed Sperling - 08 Aug, 2014 - Comments: 0

Tools Cadence rolled out a custom power integrity tool for dealing with transistor-level electromigration and IR drop with SPICE-level accuracy. It works in conjunction with the company’s existing power integrity tool for cell-level power signoff. Open-Silicon established a high-speed SerDes technology center of excellence to speed design and production of ASICs using high-speed serial co... » read more

Improving Yield Of 2.5D Designs
By Ann Mutschler - 18 Apr, 2014 - Comments: 0

While progress is being made on the packaging side of 2.5D design, more needs to be resolved when it comes to improving yields. Proponents of 2.5D present compelling benefits. Arif Rahman, a product architect at Altera, noted that the industry trend of silicon convergence is leading to multiple technologies being integrated into single-chip solutions. “2.5D/3D integration has multiple adva... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2025 SMG   |  Terms of Service  |  Privacy Policy