tag: FPGAs

Hardware Acceleration With eFPGAs
By Alok Sanghavi - 07 Jun, 2018 - Comments: 0

If integrating an embedded FPGA (eFPGA) into your ASIC or SoC design strikes you as odd, it shouldn’t. ICs have been absorbing almost every component on a circuit board for decades, starting with transistors, resistors, and capacitors –– then progressing to gates, ALUs, microprocessors, and memories. FPGAs are simply one more useful component in the tool box, available for decades and ... » read more

Speeding Up High-Frequency Trading
By Sunil Sahoo - 24 May, 2018 - Comments: 0

The High-Frequency Trading (HFT) industry has received a lot of attention during the last few years. HFT is all about speed and minimizing latency: the faster you can run trading strategies and algorithms for analyzing minute price changes and executing trade orders, the higher the probability to win over competition. So the competition in this area is very fierce with market players continuous... » read more

Resets And Reset Domain Crossings In ASIC And FPGA Designs
By Aldec - 25 Apr, 2018 - Comments: 0

This white paper explains Reset-related ASIC and FPGA design issues as well as outlines commonly-used design techniques leading to safe reset implementations. It goes on to explain about Reset Domain Crossing effects and methods to mitigate their influence on design. LINT tools provide valuable help for designers in Resets and Reset Domain Crossings verification. To download this paper, clic... » read more

Xceler Systems: Graph Architecture
By Kevin Fogarty - 19 Mar, 2018 - Comments: 0

An inventor who made foundational contributions to three key ways we move data through complex systems is developing a new type of neuromorphic chip to accelerate AI applications. Rather than try to build a computer that looks like a brain, Gautam Kavipurapu and Xceler Systems are building smaller bits that act like synapses. When the design is advanced enough and there are enough of them, t... » read more

Partitioning Challenges In Multi-FPGA Prototyping
By Aldec - 21 Feb, 2018 - Comments: 0

Multi-FPGA prototyping of ASIC & SoC designs enables the highest clock rates among emulation techniques. However, design setup for prototyping is much more complicated and challenging. In this White Paper we uncover the common challenges of partitioning design to multiple FPGAs and provide solutions that will improve your prototype quality and shorten time spent on design setup. To read ... » read more

eSilicon Builds ASIC Business On Leading-Edge Chip Design
By eSilicon - 21 Feb, 2018 - Comments: 0

How advanced application specific integrated circuits (ASIC) chip design and manufacturing for leading-edge applications such as networking and artificial intelligence can be successfully outsourced. The company which has capabilities in 2.5D packaging, high-bandwidth memories (HBM), and silicon IP for fast memories and SerDes designs. The company has many leading system companies as custome... » read more

Imperfect Silicon, Near-Perfect Security
By Kevin Fogarty - 07 Feb, 2018 - Comments: 0

Some chipmakers, under pressure to add security to rapidly growing numbers of IoT devices, have rediscovered a "fingerprinting" technique used primarily as an anti-counterfeiting measure. [getkc id="227" kc_name="Physically unclonable functions"] (PUFs) are used to assign a unique identification number based on inconsistencies in the speed with which current causes a series of logic gates to... » read more

Machine Learning’s Growing Divide
By Brian Bailey - 11 Jan, 2018 - Comments: 7

[getkc id="305" kc_name="Machine learning"] is one of the hottest areas of development, but most of the attention so far has focused on the cloud, algorithms and GPUs. For the semiconductor industry, the real opportunity is in optimizing and packaging solutions into usable forms, such as within the automotive industry or for battery-operated consumer or [getkc id="76" kc_name="IoT"] products. ... » read more

Preparing For Bigger Changes Ahead
By Ed Sperling - 21 Dec, 2017 - Comments: 0

The semiconductor industry has undergone a fundamental shift over the past year, and it's one that will redefine chipmaking over the next decade or more. While the focus is still on building the fastest, lowest-power devices, whether that's by shrinking features or packaging them into blazing-fast 2.5D or fan-out configurations, these devices are being customized for specific use cases much ... » read more

And The Winner Is…
By Brian Bailey - 21 Dec, 2017 - Comments: 0

Finding out what resonates with our readers is important, so each year I look back through the list of the best-read articles for the channels that I write for. While this simple strategy does favor articles published during the early part of the year, the fact that our readership continues to grow, partially offsets this bias. For example, in Low Power/High Performance (LPHP) a quarter of the ... » read more

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