Chip Industry Week in Review


AI featured big at this week's Design Automation Conference (DAC) in San Francisco. Dozens of companies featured AI-related tools (see product section below), as well as significant improvements to existing tools and some entirely new approaches for designing chips. Among the highlights: Siemens unveiled an AI-enhanced toolset for the EDA design flow that enables customers to integrate the... » read more

Chip Industry’s Technical Paper Roundup: Mar. 21


New technical papers recently added to Semiconductor Engineering’s library: [table id=88 /] If you have research papers you are trying to promote, we will review them to see if they are a good fit for our global audience. At a minimum, papers need to be well researched and documented, relevant to the semiconductor ecosystem, and free of marketing bias. There is no cost involved for us ... » read more

Evaluation of the Thermomechanical Reliability of Electronic Packages Using Virtual Prototyping


A new technical paper titled "Design Optimization by Virtual Prototyping Using Numerical Simulation to Ensure Thermomechanical Reliability in the Assembly and Interconnection of Electronic Assemblies" was published by Fraunhofer ENAS. Abstract "A methodology is presented that allows the evaluation of the thermomechanical reliability of electronic packages using “virtual prototyping.” He... » read more

Waiting for Porous Low-k


I'm working on a longer article on low-k dielectric integration, but in the meantime I wanted to pass along an observation from Joubert Olivier of LTM-CNRS, in his presentation at the Materials Research Society Spring Meeting. Asked about the prospects for low-k integration, he reminded the audience that even if an integration scheme is able to achieve good selectivity between the hard mask ... » read more