tag: Fraunhofer IIS/EAS

Failure Analysis Becoming Critical To Reliability
By Ed Sperling - 11 Feb, 2020 - Comments: 0

Failure analysis is rapidly becoming a complex, costly and increasingly time-consuming must-do task as demand rises for reliability across a growing range of devices used in markets ranging from automotive to 5G. From the beginning, failure analysis has been about finding out what went wrong in semiconductor design and manufacturing. Different approaches, tools and equipment have improved ov... » read more

Making Sure RISC-V Designs Work As Expected
By Ann Mutschler - 30 Jan, 2020 - Comments: 0

The RISC-V instruction set architecture is attracting attention across a wide swath of markets, but making sure devices based on the RISC-V ISA work as expected is proving as hard, if not harder, than other commercially available ISA-based chips. The general consensus is that open source lacks the safety net of commercially available IP and tools. Characterization tends to be generalized, ra... » read more

How Chips Age
By Ed Sperling - 20 Jan, 2020 - Comments: 1

Andre Lange, group manager for quality and reliability at Fraunhofer IIS’ Engineering of Adaptive Systems Division, talks about circuit aging, whether current methods of predicting reliability are accurate for chips developed at advanced process nodes, and where additional research is needed. » read more

Making 3D Structures And Packages More Reliable
By Ed Sperling - 14 Jan, 2020 - Comments: 0

The move to smaller vertical structures and complex packaging schemes is straining existing testing approaches, particularly in heterogeneous combinations on a single chip and in multi-die packages. The complexity of these devices has exploded with the slowdown in scaling, as chipmakers turn to architectural solutions and new transistor structures rather than just relying on shrinking featur... » read more

Managing Power Dynamically
By Ann Mutschler - 18 Dec, 2019 - Comments: 1

Design teams are beginning to consider dynamic power management techniques as a way of pushing the limits on performance and low power, leveraging approaches that were sidelined in the past because they were considered too difficult to deploy. Dynamic voltage and frequency scaling (DVFS), in particular, has resurfaced as a useful approach. Originally intended to dynamically balance performan... » read more

Defining And Improving AI Performance
By Brian Bailey - 12 Dec, 2019 - Comments: 2

Many companies are developing AI chips, both for training and for inference. Although getting the required functionality is important, many solutions will be judged by their performance characteristics. Performance can be measured in different ways, such as number of inferences per second or per watt. These figures are dependent on a lot of factors, not just the hardware architecture. The optim... » read more

Reducing Data At The Source
By Ed Sperling - 18 Nov, 2019 - Comments: 0

Jens Döge, group manager for image acquisition and processing in Fraunhofer IIS’ Engineering of Adaptive Systems Division, talks about how to slash the amount of data that needs to be sent to the cloud or edge for processing by focusing only on the regions of interest in an image, and how that reduces the cost of moving that data. » read more

Power Complexity On The Rise
By Ann Mutschler - 14 Nov, 2019 - Comments: 0

New chip architectures and custom applications are adding significant challenges to chip design and verification, and the problems are becoming much more complex as low power is added into the mix. Power always has been a consideration in design, but in the past it typically involved different power domains that were either on, off, or in some level of sleep mode. As hardware architectures s... » read more

Using Emulators For Power/Performance Tradeoffs
By Ann Mutschler - 10 Oct, 2019 - Comments: 1

Emulation is becoming the tool of choice for power and performance tradeoffs, scaling to almost unlimited capacity for complex chips used in data centers, AI/ML systems and smart phones. While emulation has long been viewed as an important but expensive asset for chipmakers trying to verify and debug chips, it is now viewed as an essential component for design optimization and analysis much ... » read more

Open ISAs Gaining Traction
By Ann Mutschler - 26 Sep, 2019 - Comments: 0

Open instruction set architectures are starting to gain a foothold, often in combination with other processors, as chipmakers begin to add more specialized compute elements and more flexibility into their designs. There are a number of these open ISAs available today, including Power, MIPS, and RISC-V, and there are a number of permutations and tools available for sale based on those archite... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2025 SMG   |  Terms of Service  |  Privacy Policy