tag: Fraunhofer IIS EAS

Toward High-End Fan-Outs
By Ed Sperling - 05 Mar, 2018 - Comments: 1

Foundries and OSATs are working on more advanced fan-outs, including some with vertically stacked die inside the package, filling a middle ground between lower-cost fan-outs and systems in package on one side and 2.5D and 3D-ICs on the other. These new [getkc id="202" kc_name="fan-outs"] have denser interconnects than previous iterations, and in some cases they include multiple routing layer... » read more

Chip Aging Accelerates
By Ed Sperling - 14 Feb, 2018 - Comments: 1

Reliability is becoming an increasingly important proof point for new chips as they are rolled out in new markets such as automotive, cloud computing and industrial IoT, but actually proving that a chip will function as expected over time is becoming much more difficult. In the past, reliability generally was considered a foundry issue. Chips developed for computers and phones were designed ... » read more

Avoiding Down Times: Monitoring, Diagnostics And Troubleshooting Of Industrial Wireless Systems
By Fraunhofer IIS/EAS - 07 Feb, 2018 - Comments: 0

The ever-growing proliferation of wireless devices and technologies used for Internet of Things (IoT) applications, such as patient monitoring, military surveillance, and industrial automation and control, has created an increasing need for methods and tools for connectivity prediction, information flow monitoring, and failure analysis to increase the dependability of the wireless network. Inde... » read more

Turning Down The Power
By Jeff Dorsch - 11 Jan, 2018 - Comments: 0

Chip and system designers are giving greater weight to power issues these days. But will they inevitably hit a wall in accounting for ultra-low-power considerations? Performance, power, and area are the traditional attributes in chip design. Area was originally the main priority, with feature sizes constantly shrinking according to Moore's Law. Performance was in the saddle for many years. M... » read more

Mixed-Signal Issues Worse At 10/7nm
By Ann Mutschler - 03 Jan, 2018 - Comments: 1

Despite increasingly difficulty in scaling digital logic to 10/7nm, not all designs at the leading edge are digital. In fact, there are mixed-signal components in designs at almost all nodes down to 10/7nm. This may seem surprising because analog scaling has been an issue since about 90nm, but these are not traditional analog components. Analog IP increasingly includes highly integrated, mix... » read more

The Trouble With Models
By Ed Sperling - 20 Dec, 2017 - Comments: 0

Models are becoming more difficult to develop, integrate and utilize effectively at 10/7nm and beyond as design complexity, process variation and physical effects add to the number of variables that need to be taken into account. Modeling is a way of abstracting the complexity in various parts of the semiconductor design, and there can be dozens of models required for complex SoCs. Some are ... » read more

Body Biasing For Analog Design
By Fraunhofer IIS/EAS - 13 Dec, 2017 - Comments: 0

This paper presents the practical application of body biasing control of ultra-deep submicron FD-SOI technologies for analog and mixed-signal designs. The body biasing control is dedicated for dynamic control of the trade- off between speed vs. power consumption for advanced digital circuits. However, in this work we focus on trading-off and improvement of analog circuit performances. Three dif... » read more

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