tag: functional test

Functional Compaction for Functional Test Sequences (Purdue University, I. Pomeranz)
By Technical Paper Link - 17 Jul, 2024 - Comments: 0

A new technical paper titled "Functional Compaction for Functional Test Sequences" was published by IEEE Fellow Irith Pomeranz at Purdue University. Abstract: "The occurrence of silent data corruption because of hardware defects in large scale data centers points to the advantages of applying functional test sequences to detect hardware defects that escape scan-based tests. When using funct... » read more

What’s Missing In Test
By Anne Meixner - 19 Jun, 2024 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss how functional test content is brought up at first silicon, and the balance between ATE and system-level testing, with Klaus-Dieter Hilliges, V93000 platform extension manager at Advantest Europe; Robert Cavagnaro, fellow in the Design Engineering Group at Intel (responsible for manufacturing and test strategy of data center... » read more

Doing More At Functional Test
By Anne Meixner - 14 May, 2024 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss the increasing importance of functional test, especially in high-performance computing, with Klaus-Dieter Hilliges, V93000 platform extension manager at Advantest Europe; Robert Cavagnaro, fellow in the Design Engineering Group at Intel (responsible for manufacturing and test strategy of data center products); Nitza Basoco, tec... » read more

Device Validation: The Ultimate Test Frontier
By Dave Armstrong - 11 Apr, 2023 - Comments: 0

This article is a condensed version of an article that appeared in the November/December 2022 issue of Chip Scale Review. Adapted with permission. Read the original article at https://chipscalereview.com/wp-content/uploads/flipbook/30/book.html, p. 26. In the early days of space exploration, spacecraft were manned by small teams of astronauts, most of whom were experienced test pilots who ... » read more

More Manufacturing Issues, More Testing
By Ed Sperling - 08 Feb, 2022 - Comments: 0

Douglas Lefever, CEO of Advantest America, sat down with Semiconductor Engineering to talk about changes in test, the impact of advanced packaging, and business changes that are happening across the flow. What follows are excerpts of that discussion. SE: What are the big changes ahead in test? Lefever: It's less about inflection points and more like moving from algebra to calculus in the ... » read more

Remotely Performing IC Validation
By Tommy Mullane - 20 May, 2020 - Comments: 0

One of the key stages in designing any chip is the testing you do when you get the first silicon back. This is where you finally see the results of all your careful work and determine whether the chip is performing as designed, and as simulation told you it would. This is known as IC validation. The focus of validation is on functional test – checking that the chip in silicon meets the origin... » read more

System-Level Test: Where Does It Fit?
By Astronics - 17 Sep, 2018 - Comments: 0

Our second C-Brief discusses where system-level test (SLT) best fits into your semiconductor test workflow. With automated testing equipment (ATE), a traditional workflow may consist of: Wafer sort (WS) Burn-in after packaging (BI) Combination of structural testing (ST) and functional testing (FT). As demands on high-volume manufacturing shift in response to wider industry and com... » read more

Test Challenges Grow
By Mark LaPedus - 27 May, 2014 - Comments: 3

Semiconductor Engineering sat down to discuss current and future test challenges with Dave Armstrong, director of business development at Advantest; Steve Pateras, product marketing director for Silicon Test Solutions at Mentor Graphics; Robert Ruiz, senior product marketing manager at Synopsys; Mike Slessor, president of FormFactor; and Dan Glotter, chief executive of Optimal+. SE: In our ... » read more

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