tag: GAA

Improving Power and Speed in GAA-NS FETs
By Technical Paper Link - 11 Nov, 2024 - Comments: 0

A new technical paper titled "Design Decoupling of Inner-and Outer-Gate Lengths in Nanosheet FETs for Ultimate Scaling" was published by researchers at Belgium Research Center, Huawei Technologies and Global TCAD Solutions. Abstract: "Using a full design-technology-co-optimization (DTCO) methodology, we show the advantages of design decoupling of inner -and outer-gates in gate-all-around ... » read more

Legacy Process Nodes Going Strong
By Bryon Moyer - 23 Jul, 2024 - Comments: 0

While all eyes tend to focus on the leading-edge silicon nodes, many mature nodes continue to enjoy robust manufacturing demand. Successive nodes stopped reducing die cost at around the 20nm node. “In the finFET era of processes, esoteric process requirements necessary to move technology forward with each generation have added significant cost and complexity,” explained Andrew Appleby, p... » read more

Chip Industry Week In Review
By The SE Staff - 03 May, 2024 - Comments: 0

Samsung and Synopsys collaborated on the first production tapeout of a high-performance mobile SoC design, including CPUs and GPUs, using the Synopsys.ai EDA suite on Samsung Foundry's gate-all-around (GAA) process. Samsung plans to begin mass production of 2nm process GAA chips in 2025, reports BusinessKorea. UMC developed the first radio frequency silicon on insulator (RF-SOI)-based 3D IC ... » read more

3D NAND: Scenarios For Scaling & Stacking
By Technical Paper Link - 25 Aug, 2022 - Comments: 0

A new research paper titled "Impact of Stacking-Up and Scaling-Down Bit Cells in 3D NAND on Their Threshold Voltages" was published by researchers at Sungkyunkwan University and Korea University. Abstract "Over the past few decades, NAND flash memory has advanced with exponentially-increasing bit growth. As bit cells in 3D NAND flash memory are stacked up and scaled down together, some pote... » read more

FEOL Nanosheet Process Flow & Challenges Requiring Metrology Solutions (IBM Watson)
By Technical Paper Link - 08 Jul, 2022 - Comments: 0

New technical paper titled "Review of nanosheet metrology opportunities for technology readiness," from researchers at IBM Thomas J. Watson Research Ctr. (United States). Abstract (partial): "More than previous technologies, then, nanosheet technology may be when some offline techniques transition from the lab to the fab, as certain critical measurements need to be monitored in real time. T... » read more

Synchrotron S-ray Diffraction-based Non-destructive Nanoscale Mapping of Si/SiGe Nanosheets for GAA structures
By Technical Paper Link - 13 Jun, 2022 - Comments: 0

New research paper titled "Mapping of the mechanical response in Si/SiGe nanosheet device geometries" from researchers at IBM T.J. Watson Research Center and Brookhaven National Laboratory. Sponsored by U.S. DOE. Abstract "The performance of next-generation, nanoelectronic devices relies on a precise understanding of strain within the constituent materials. However, the increased flexibilit... » read more

Week In Review: Manufacturing, Test
By Mark LaPedus - 08 Oct, 2021 - Comments: 0

Government policy Hoping to resolve the ongoing worldwide chip shortage situation, the U.S. Department of Commerce late last month launched a “request for information (RFI)” initiative, which involved sending questionnaires to various semiconductor companies. The U.S. government is asking all parts of the supply chain – producers, consumers, and intermediaries – to voluntarily share in... » read more

Dynamic Flash Memory with Dual Gate Surrounding Gate Transistor (SGT)
By Technical Paper Link - 03 Sep, 2021 - Comments: 0

Abstract: "This paper proposes an ultra-scaled memory device, called `Dynamic Flash Memory (DFM)'. With a dual-gate Surrounding Gate Transistor (SGT), a capacitorless 4F2 cell can be achieved. Similar to DRAM [1], refresh is needed, but high speed block refresh can improve the duty ratio. Analogous to Flash [2], three fundamental operations of “0” Erase, “1” Program, and Read are nee... » read more

Inner Spacer Engineering to Improve Mechanical Stability in Channel-Release Process of Nanosheet FETs
By Technical Paper Link - 28 Aug, 2021 - Comments: 0

  Abstract "Mechanical stress is demonstrated in the fabrication process of nanosheet FETs. In particular, unwanted mechanical instability stemming from gravity during channel-release is covered in detail by aid of 3-D simulations. The simulation results show the physical weakness of suspended nanosheets and the impact of nanosheet thickness. Inner spacer engineering based on geometr... » read more

From FinFETs To Gate-All-Around
By Nerissa Draeger - 19 Nov, 2020 - Comments: 0

When they were first commercialized at the 22 nm node, finFETs represented a revolutionary change to the way we build transistors, the tiny switches in the “brains” of a chip. As compared to prior planar transistors, the fin, contacted on three sides by the gate, provides much better control of the channel formed within the fin. But, finFETs are already reaching the end of their utility as... » read more

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