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3D NAND: Scenarios For Scaling & Stacking

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A new research paper titled “Impact of Stacking-Up and Scaling-Down Bit Cells in 3D NAND on Their Threshold Voltages” was published by researchers at Sungkyunkwan University and Korea University.

Abstract
“Over the past few decades, NAND flash memory has advanced with exponentially-increasing bit growth. As bit cells in 3D NAND flash memory are stacked up and scaled down together, some potential challenges should be investigated. In order to reasonably predict those challenges, a TCAD (technology computer-aided design) simulation for 3D NAND structure in mass production has been run. By aggressively stacking-up and scaling-down bit cells in a string, the structure of channel hole was varied from a macaroni to nanowire. This causes the threshold voltage difference (ΔVth ) between the top cell and bottom cell in the same string. In detail, ΔVth between the top cell and bottom cell mostly depends on the xy-scaling, but the way how ΔVth  is affected is not very dependent on the stack height.”

Find the technical paper here. Published July 2022.

Lee, D.; Shin, C. Impact of Stacking-Up and Scaling-Down Bit Cells in 3D NAND on Their Threshold Voltages. Micromachines 2022, 13, 1139. https://doi.org/10.3390/mi13071139.

 

Source: “Impact of Stacking-Up and Scaling-Down Bit Cells in 3D NAND on Their Threshold Voltages” figure 2.

 

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