tag: GlobalFoundries

Boosting Yield With Layout Awareness
By Ed Sperling - 26 Apr, 2012 - Comments: 0

By Ann Steffora Mutschler Yield. Just the word can make many engineers cringe and hide in their cubicles—especially with manufacturing problems and excessive power during test increasing causing failures. But the combination of physical data with diagnostics engines may be the light at the end of the tunnel, allowing for easier pinpointing of defects. There are many reasons why a chip fai... » read more

New Processes Define New Power Plans
By Ed Sperling - 05 Apr, 2012 - Comments: 0

By Pallab Chatterjee FinFETs, stacked die, heterogeneous interposers, TSVs, 450mm wafers, new interconnects and everything with MEMs and sensors is what the last few weeks have brought. A number of major announcements, technology releases, conference updates have identified these technologies as the future of IC design. At ISQED, Robert Geer, chief academic officer at the College of Nanosca... » read more

FinFET Vs. Tri-Gate
By Barry Pangrle - 05 Apr, 2012 - Comments: 0

By Barry Pangrle A large portion of the Common Platform Technology Forum, recently held in Santa Clara, was dedicated to presentations about 14nm process technologies and FinFETS. If you missed the event and are interested, many of the presentations are available from a link off of the Common Platform home page. Dick James wrote a nice article about GlobalFoundries’ claim that its FinFETS ar... » read more

Intel Turns Up Heat in Silicon Foundry Business
By Ed Sperling - 04 Apr, 2012 - Comments: 0

By Mark LaPedus Intel Corp. continues to make waves in the foundry arena. The chip giant has recently announced three new and major customers within its embryonic foundry business. Some speculate there are more customers on the horizon, reportedly including a rumored on-and-off again foundry deal with Apple Inc. At this point, Intel is a niche player in the foundry business, as the compan... » read more

Consortium Results (Part 3 of 3): 20nm FDSOI Comes Out Way Ahead
By Various Writers - 27 Mar, 2012 - Comments: 0

The results of the most recent SOI Consortium benchmarking study detail the interest of planar FD-SOI as early as the 28nm and 20nm technology nodes, in terms of performance, power and manufacturability. This 3-part blog series looks further at some of the implications. ~~ The SOI Industry Consortium announcement at the end of the year provided silicon proof that FD-SOI handily bea... » read more

New Winners And Losers
By Ed Sperling - 22 Mar, 2012 - Comments: 0

The realignment of the semiconductor industry has begun, most of it beneath the radar screen. In a disaggregated supply chain, any piece in isolation looks insignificant. But taken together, these shifts begin to paint a picture of a broad realignment and refocusing of the entire industry that ultimately will cement the fortunes of some and create new winners and losers out of others. The fi... » read more

FD-SOI – Consortium Results (Part 2 of 3): Power and Performance
By Various Writers - 21 Mar, 2012 - Comments: 0

The results of the most recent SOI Consortium benchmarking study detail the interest of planar FD-SOI as early as the 28nm and 20nm technology nodes, in terms of performance, power and manufacturability. This 3-part blog series looks further at some of the implications. ~~ Fully depleted transistor architectures such as Planar FD-SOI, FinFETs (which is also a fully-depleted technolog... » read more

FD-SOI – Recent Consortium Results (Part 1 of 3): Manufacturing
By Various Writers - 05 Mar, 2012 - Comments: 0

The most recent SOI Consortium benchmarking study regarding 28nm and 20nm FD-SOI results (silicon-calibrated simulations at the 28nm node of complex circuits including ARM cores and DDR3 memory controllers) covered a lot of ground. This post is part 1 of a 3-part blog series that will be highlighting key points with respect to: 1. manufacturing; 2. power & performance; 3. 20nm benchmarking ... » read more

Different Tradeoffs
By Ed Sperling - 23 Feb, 2012 - Comments: 0

By Ed Sperling The push to “smaller, faster and cheaper” hasn’t changed since ICs were first introduced, but the context for those requirements is beginning to shift—with enormous consequences. What was once done on multiple chips continue to migrate to a single chip or package because of cost, but in some cases the decisions about goes where go well beyond an individual device to i... » read more

Different Tradeoffs
By Ed Sperling - 23 Feb, 2012 - Comments: 0

By Ed Sperling The push to “smaller, faster and cheaper” hasn’t changed since ICs were first introduced, but the context for those requirements is beginning to shift—with enormous consequences. What was once done on multiple chips continue to migrate to a single chip or package because of cost, but in some cases the decisions about goes where go well beyond an individual device to i... » read more

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