Node Skipping Reaches New Heights


By Mark LaPedus For years, silicon foundries have rolled out their respective leading-edge processes roughly on a two-year cadence. The long-standing goal has been to keep foundry customers on a competitive price, power and performance curve. But as leading-edge chipmakers move from the 28nm node and beyond, the predictable process progression is changing. And the phenomenon of “node skip... » read more

Facing Up To RC Delay


y Ed Sperling Resistance and capacitance delays have always been someone else’s problem to solve at some fuzzy process node in the future, and for the most part manufacturers and equipment makers have done a wizard-like job of making this problem go away. They can’t make it disappear anymore, though, and beginning at 14nm and beyond RC delay is becoming more than just an annoyance. The ... » read more

Mobile Memory Madness


By Mark LaPedus The insatiable thirst for more bandwidth in smartphones, tablets and other devices has prompted an industry standards body to revamp its mobile memory interface roadmap. As part of the changes, the Joint Electron Devices Engineering Council (JEDEC) has scaled back the initial version of Wide I/O technology and pushed out the introduction date of a true 3D stacked architectur... » read more

The Growing Integration Challenge


By Ed Sperling As the number of processors and the amount of memory and IP on a chip continues to skyrocket, so does the challenge for integrating all of this stuff on a single die—or even multiple dies in the same package. There are a number of reasons why it’s getting more difficult to make all of these IP blocks work together. First of all, nothing ever stands still in design. As a r... » read more

New Incentives For Lowering Power


By Ed Sperling Despite all the focus by design teams on lowering power over the past few years, in many applications power is still the last consideration for many companies in the power-performance-area equation. That’s beginning to change, however, even for applications that in the past have not been particularly power-sensitive. There are several reasons for this shift. No. 1 on the li... » read more

Roundtable: Lower-Power Chips


Low Power-High Performance Engineering talks about problems in low-power design with Richard Trihy of GlobalFoundries, Leah Clark of Broadcom, Qi Wang of Cadence and Venki Venkatesh of Atrenta. [youtube vid=cD560pgEegk] » read more

Experts At The Table: Obstacles In Low-Power Design


By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss low-power design with with Leah Clark, associate technical director at Broadcom; Richard Trihy, director of design enablement at GlobalFoundries; Venki Venkatesh, engineering director at Atrenta; and Qi Wang, technical marketing group director at Cadence. What follows are excerpts of that conversation. LPHP: What are ... » read more

Changes Ahead


Semiconductor Manufacturing & Design talks with GlobalFoundries EVP Mike Noonen about future challenges in IC manufacturing, the future of stacked die and ecosystem challenges ahead. [youtube vid=Wdp9JYvBeSk] » read more

Experts At The Table: IC Manufacturing Challenges


By Mark LaPedus Semiconductor Manufacturing & Design sat down to discuss future manufacturing challenges with Carlos Mazure, chief technical officer at Soitec; Jeff Hebb, vice president of laser product marketing at Ultratech; Markus Wimplinger, corporate technology development and IP director at EV Group; and Girish Dixit, vice president of the customer integration center and process inte... » read more

ST’s FD-SOI Tech Available to All Through GF


Posted by Adele Hars, Editor-in-Chief, Advanced Substrate News ~  ~ In the spring of 2012, STMicroelectronics announced the company would be manufacturing ST-Ericsson’s next-generation (and very successful) NovaThor ARM-based smartphone/tablet processors using 28nm FD-SOI process technology. With first samples coming out this fall, ASN talks to Jean-Marc Chery, Executive Vice Pres... » read more

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