tag: hardware security

Suppressing Power Side-Channel Attacks: A HW/SW Design For Resource-Constrained IoT Devices
By Technical Paper Link - 12 Mar, 2024 - Comments: 0

A technical paper titled “Hardware/Software Cooperative Design Against Power Side-Channel Attacks on IoT Devices” was published by researchers at Tokyo Institute of Technology and the University of Electro-Communications. Abstract: "With the growth of Internet of Things (IoT) era, the protection of secret information on IoT devices is becoming increasingly important. For IoT devices, atta... » read more

K-Fault Resistant Partitioning To Assess Redundancy-Based HW Countermeasures To Fault Injections
By Technical Paper Link - 07 Mar, 2024 - Comments: 0

A technical paper titled “Fault-Resistant Partitioning of Secure CPUs for System Co-Verification against Faults” was published by researchers at Université Paris-Saclay, Graz University of Technology, lowRISC, University Grenoble Alpes, Thales, and Sorbonne University. Abstract: "To assess the robustness of CPU-based systems against fault injection attacks, it is necessary to analyze the... » read more

An Analytical EM Model For IC Shielding Against HW Attacks
By Technical Paper Link - 05 Mar, 2024 - Comments: 0

A technical paper titled “Refined Analytical EM Model of IC-Internal Shielding for Hardware-Security and Intra-Device Simulative Framework” was published by researchers at Bar-Ilan University and Rafael Defense Systems. Abstract: "Over the past two decades, the prominence of physical attacks on electronic devices, designed to extract confidential information, has surged. These attacks exp... » read more

Broad Impact From Accelerating Tech Cycles
By Ed Sperling - 21 Feb, 2024 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss the impact of leading edge technologies such as generative AI in data centers, AR/VR, and security architectures for connected devices, with Michael Kurniawan, business strategy manager at Accenture; Kaushal Vora, senior director and head of business acceleration and ecosystem at Renesas Electronics; Paul Karazuba, vice preside... » read more

HW Security Bug Characteristics in Google’s OpenTitan Silicon Root Of Trust Project 
By Technical Paper Link - 15 Feb, 2024 - Comments: 0

A technical paper titled “An Investigation of Hardware Security Bug Characteristics in Open-Source Projects” was published by researchers at NYU Tandon School of Engineering and University of Calgary. Abstract: "Hardware security is an important concern of system security as vulnerabilities can arise from design errors introduced throughout the development lifecycle. Recent works have pro... » read more

Radix Coverage for Hardware Common Weakness Enumeration (CWE) Guide (updated)
By Cycuity (Formerly Tortuga Logic) - 31 Jan, 2024 - Comments: 0

MITRE’s hardware Common Weakness Enumeration (CWE) database aggregates hardware weaknesses that are the root causes of vulnerabilities in deployed parts. In this 100+ page guide, each CWE is listed along with a Radix template Security Rule that can be filled in with design-specific signals and used as a baseline test for the respective CWE. To learn more about a specific CWE, follow the li... » read more

How To Stop Row Hammer Attacks
By Ed Sperling - 30 Jan, 2024 - Comments: 0

Row hammer is a well-publicized target for cyberattacks on DRAM, and there have been attempts to stop these attacks in DDR4 and DDR5, but with mixed results. The problem is that as density increases, distance decreases, making it more likely that flipped bit cell in one row can disturb a bit cell in another, and that bits flipped across an entire row can flip another row. Steven Woo, fellow and... » read more

Challenges And Innovations Of HW Security And Trust For Chiplet-Based 2.5D and 3D ICs
By Technical Paper Link - 04 Jan, 2024 - Comments: 0

A technical paper titled “On hardware security and trust for chiplet-based 2.5D and 3D ICs: Challenges and Innovations” was published by researchers at STMicroelectronics Crolles (ST-CROLLES), Département Systèmes et Circuits Intégrés Numériques (DSCIN), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), and Laboratoire Systèm... » read more

SystemC-based Power Side-Channel Attacks Against AI Accelerators (Univ. of Lubeck)
By Technical Paper Link - 21 Dec, 2023 - Comments: 0

A new technical paper titled "SystemC Model of Power Side-Channel Attacks Against AI Accelerators: Superstition or not?" was published by researchers at Germany's University of Lubeck. Abstract "As training artificial intelligence (AI) models is a lengthy and hence costly process, leakage of such a model's internal parameters is highly undesirable. In the case of AI accelerators, side-chann... » read more

Nanoscale Reconfigurable Si Transistors (TU Wien, CNRS, UNC)
By Technical Paper Link - 20 Dec, 2023 - Comments: 0

A new technical paper titled "Nanoscale Reconfigurable Si Transistors: From Wires to Sheets and Unto Multi-Wire Channels" was published by researchers at TU Wien, CNRS, and University of North Carolina at Chapel Hill. Abstract: "In this work, bottom-up Al–Si–Al nanowire (NW) heterostructures are presented, which act as a prototype vehicle toward top-down fabricated nanosheet (NS) and ... » read more

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