Statistical Model Checking As An Evaluation Tool of Microarchitectural Side Channels (Duke, Harvard, Univ. of Florida)


A new technical paper titled "Rigorous Evaluation of Microarchitectural Side-Channels with Statistical Model Checking" was published by researchers at Duke University, Harvard University and University of Florida. Abstract "Rigorous quantitative evaluation of microarchitectural side channels is challenging for two reasons. First, the processors, attacks, and defenses often exhibit probabili... » read more

Why Anti-Tamper Sensors Matter: Delivering A Comprehensive Security Solution


If your device processes valuable data, controls a critical function, or connects to a wider network, it’s a target. Attackers don’t just try to break software; they increasingly physically tamper with hardware: probing, fault injecting, or opening enclosures to bypass protections and extract secrets. The consequences range from IP theft and fraud to orchestrated downtime across fleets ... » read more

The Competitive Advantage Of SRAM PUF Technology


By Vincent van der Leest and Geert-Jan Schrijen In the article from 2024, "SRAM PUF: The Secure Silicon Fingerprint", we explored the fundamentals of SRAM-based Physical Unclonable Functions (PUFs) and their role as a secure, cost-effective, and scalable solution for cryptographic (root) key generation and storage. SRAM PUF technology leverages the unique physical properties of silicon to c... » read more

Distributed Authentication Framework Leveraging Multi-Party Computation In A Scalable Tree-Based Architecture (Univ. of Central Florida, Louisiana State)


A new technical paper titled "AuthenTree: A Scalable MPC-Based Distributed Trust Architecture for Chiplet-based Heterogeneous Systems" was published by researchers at University of Central Florida and Louisiana State University. Abstract "The rapid adoption of chiplet-based heterogeneous integration is reshaping semiconductor design by enabling modular, scalable, and faster time-to-market s... » read more

New Spectre Branch Target Injection, Spectre-BTI, Attack Primitives On CPUs (ETH Zurich)


A new technical paper titled “VMSCAPE: Exposing and Exploiting Incomplete Branch Predictor Isolation in Cloud Environments” was published by researchers at ETH Zurich. Abstract “Virtualization is a cornerstone of modern cloud infrastructures, providing the required isolation to customers. This isolation, however, is threatened by speculative execution attacks which the CPU vendors att... » read more

Security Technical Paper Roundup: Sept. 30


A number of hardware security-related technical papers were presented at the August 2025 USENIX Security Symposium. The organization provides open access research, and the presentation slides and papers are free to the public. Topics include side-channel attacks and defenses, embedded security, fuzzing, fault injection, rowhammer, and more. Here are some highlights with associated links: [ta... » read more

Undervolting Attack That Exploits The Vulnerability Of Chips During Brownout Conditions (Worcester Polytechnic, RUB)


A new technical paper titled "Chypnosis: Stealthy Secret Extraction using Undervolting-based Static Side-channel Attacks" was published by researcher at Worcester Polytechnic Institute and Ruhr University Bochum. Abstract: "Static side-channel analysis attacks, which rely on a stopped clock to extract sensitive information, pose a growing threat to embedded systems' security. To protect a... » read more

Compromising Spectre v2 HW Mitigations By Exploiting BPRC (ETH Zurich)


A new technical paper titled "Branch Privilege Injection: Compromising Spectre v2 Hardware Mitigations by Exploiting Branch Predictor Race Conditions" was published by researchers at ETH Zurich. Presented at USENIX Security Symposium in August 2025. Abstract "Modern branch predictors prevent Spectre v2 attacks by associating predictions with the privilege domain they should be restricted to... » read more

3D-Stacked HBM Architecture Susceptibility To Thermal Attacks (NC A&T State, New Mexico State)


A new technical paper titled "On the Thermal Vulnerability of 3D-Stacked High-Bandwidth Memory Architectures" was published by researchers at North Carolina A&T State University and New Mexico State University. Abstract "3D-stacked High Bandwidth Memory (HBM) architectures provide high-performance memory interactions to address the well-known performance challenge, namely the memory wal... » read more

HW Security: 2.5D and 3D Technologies Provide Opportunities in Designing Secure Systems (UCSB, Columbia)


A new technical paper titled "Leveraging 3D Technologies for Hardware Security: Opportunities and Challenges" was published by researchers at the University of California, Santa Barbara and Columbia University. Abstract "3D die stacking and 2.5D interposer design are promising technologies to improve integration density, performance and cost. Current approaches face serious issues in dealin... » read more

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