tag: Helic

Week In Review: Design, Low Power
By Jesse Allen - 25 Jan, 2019 - Comments: 0

M&A Ansys will acquire Helic, a provider of electromagnetic crosstalk analysis and signoff tools. Founded in 2000, Helic's tools included pre- and post-LVS EM modeling, inductor synthesis and modeling, and analysis of crosstalk risk. The company's technology will be integrated into a solution for on-chip, 3D integrated circuit and chip-package-system electromagnetics and noise analysis. Th... » read more

Power Issues Rising For New Applications
By Ann Mutschler - 21 Jan, 2019 - Comments: 0

Managing power in chips is becoming more difficult across a wide range of applications and process nodes, forcing chipmakers and systems companies to rethink their power strategies and address problems much earlier than in the past. While power has long been a major focus in the mobile space, power-related issues now are spreading well beyond phones and laptop computers. There are several re... » read more

How to Make Sure IP will Float in the Rough SoC Sea
By Magdy Abadir - 19 Dec, 2018 - Comments: 0

Today a typical SoC includes hundreds of instances of IP modules both digital and analog. These IPs are typically verified individually by the vendors. The burden of guaranteeing functionality when placed in the midst of a monster SoC is typically left to the SoC owner. With increasing frequencies, tighter margins, denser integrated circuits, new devices and materials, the task of verifying So... » read more

The Cost Of Accuracy
By Brian Bailey - 13 Dec, 2018 - Comments: 0

How accurate does a system need to be, and what are you willing to pay for that accuracy? There are many sources of inaccuracy throughout the development flow of electronic systems, most of which involve complex tradeoffs. Inaccuracy leaves an impact on your design in ways you are not even aware of, hidden by best practices or guard-banding. EDA tools also inject some inaccuracy. As the i... » read more

How To Improve Analog Design Reuse
By Ann Mutschler - 14 Nov, 2018 - Comments: 0

Digital circuit design is largely automated today, but most analog components still are designed manually. This may change soon. As analog design grows increasingly complex and error-prone, design teams and tool vendors are focusing on how to automate as much of the design of analog circuits as possible. Analog design is notoriously difficult and varied. It can include anything from power ma... » read more

Why Chips Die
By Brian Bailey - 12 Nov, 2018 - Comments: 4

Semiconductor devices contain hundreds of millions of transistors operating at extreme temperatures and in hostile environments, so it should come as no surprise that many of these devices fail to operate as expected or have a finite lifetime. Some devices never make it out of the lab and many others die in the fab. It is hoped that most devices released into products will survive until they be... » read more

Taming NBTI To Improve Device Reliability
By Ann Mutschler - 08 Nov, 2018 - Comments: 2

Negative-bias temperature instability is a growing issue at the most advanced process nodes, but it also has proven extremely difficult to tame using conventional approaches. That finally may be starting to change. NBTI is an aging mechanism in field-effect transistors that leads to a change of the characteristic curves of a transistor during operation. The result can be a drift toward unint... » read more

Week In Review: Manufacturing, Test
By Mark LaPedus - 12 Oct, 2018 - Comments: 0

Chipmakers GlobalFoundries has announced the addition of nine new partners to its RFwave Partner Program, including AkronIC, Ask Radio, Catena, University of Waterloo Centre for Intelligent Antenna and Radio Systems (CIARS), Giga Solution, Helic, Incize, Mentor Graphics and Xpeedic Technology. The RFwave Partner Program builds upon GF’s radio-frequency (RF) efforts. The new partners will pro... » read more

Power Delivery Affecting Performance At 7nm
By Brian Bailey - 11 Oct, 2018 - Comments: 4

Complex interactions and dependencies at 7nm and beyond can create unexpected performance drops in chips that cannot always be caught by signoff tools. This isn't for lack of effort. The amount of time spent trying to determine if an advanced-node chip will work after it is fabricated has been rising steadily for several process nodes. Additional design rules handle everything from variation... » read more

Parametric Analysis, Design Guidelines for mm-Wave nm CMOS Transmission Lines
By Helic - 10 Oct, 2018 - Comments: 0

This paper focuses on nm CMOS transmission line design as distributed passive elements and their application in mm-wave integrated circuits. A variety of transmission lines such as coplanar waveguides (CPWs), shielded coplanar waveguides (SCPWs), and CPW with ground are analyzed in terms of their geometry and electrical properties. The parametric analysis of the various line types is based on a... » read more

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