tag: heterogeneous design

Heterogenous Integration Creating New IP Opportunities
By Brian Bailey - 19 Jul, 2022 - Comments: 0

The design IP market has long been known for constant change and evolution, but the industry trend toward heterogenous integration and chiplets is creating some new challenges and opportunities. Companies wanting to stake out a claim in this area have to be nimble, because there will be many potential standards introduced, and they are likely to change quickly as the industry explores what is r... » read more

EDA Gaps At The Leading Edge
By Ed Sperling - 29 Jun, 2022 - Comments: 1

Semiconductor Engineering sat down to discuss why new approaches are required for heterogeneous designs, with Bari Biswas, senior vice president for the Silicon Realization Group at Synopsys; John Lee, general manager and vice president of the Ansys Semiconductor business unit; Michael Jackson, corporate vice president for R&D at Cadence; Prashant Varshney, head of product for Microsoft Azu... » read more

RF To mmWave Design For Systems
By Cadence - 23 Feb, 2022 - Comments: 0

RF-enabled next-generation communication systems and connected devices are differentiated by their performance, size, and cost. Traditionally, custom proprietary IC designs, leveraging the latest advanced-node technology, were developed to meet these product requirements. Increasingly these challenges are being met by moving beyond single IC solutions. Today’s electronic systems often integra... » read more

Debugging Embedded Applications
By Ann Mutschler - 10 Nov, 2021 - Comments: 0

Debugging embedded designs is becoming increasingly difficult as the number of observed and possible interactions between hardware and software continue to grow, and as more features are crammed into chips, packages, and systems. But there also appear to be some advances on this front, involving a mix of techniques, including hardware trace, scan chain-based debug, along with better simulation ... » read more

RISC-V’s Expanding Footprint
By Ed Sperling - 27 Aug, 2020 - Comments: 0

Zdenek Prikryl, CTO of Codasip, sat down with Semiconductor Engineering to talk about the RISC-V market, where this open instruction set architecture (ISA) is gaining ground, and what are the biggest challenges in working with this technology. SE: Where do you see the value in RISC-V? Is it for off-the-shelf processors or more customized components? Prikryl: A few years ago, RISC-V was us... » read more

Power Challenges In ML Processors
By Brian Bailey - 12 Mar, 2020 - Comments: 0

The design of artificial intelligence (AI) chips or machine learning (ML) systems requires that designers and architects use every trick in the book and then learn some new ones if they are to be successful. Call it style, call it architecture, there are some designs that are just better than others. When it comes to power, there are plenty of ways that small changes can make large differences.... » read more

Distributed Design Implementation
By Ed Sperling - 04 Dec, 2019 - Comments: 0

PV Srinivas, group director for R&D at Synopsys, talks about the impact of larger chips and increasing complexity on design productivity, why divide-and-conquer doesn’t work so well anymore, and how to reduce the number of blocks that need to be considered to achieve faster timing closure and quicker time to market. » read more

Who’s Watching The Supply Chain?
By Ed Sperling - 17 Oct, 2019 - Comments: 0

Every company developing chips at the most advanced process nodes these days is using different architectures and heterogeneous processing and memory elements. There simply is no other way to get the kind of power/performance improvements needed to justify the expense of moving to a new process node. So while they will reap the benefits of traditional scaling, that alone is no longer enough. ... » read more

Process Window Optimization
By Ed Sperling - 07 Aug, 2019 - Comments: 0

David Fried, vice president of computational products at Lam Research, examines increasing process variation and interactions between various types of variation, why different approaches are necessary to improve yield and continue scaling. » read more

CEO Outlook: It Gets Much Harder From Here
By Ed Sperling - 03 Jun, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss what's changing across the semiconductor industry with Wally Rhines, CEO emeritus at Mentor, a Siemens Business; Jack Harding, president and CEO of eSilicon; John Kibarian, president and CEO of PDF Solutions; and John Chong, vice president of product and business development for Kionix. What follows are excerpts of that discussion, which was held in... » read more

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