中文 English

RISC-V’s Expanding Footprint

Codasip’s CTO talks about the market opportunities and technical challenges of working with the open-source ISA

popularity

Zdenek Prikryl, CTO of Codasip, sat down with Semiconductor Engineering to talk about the RISC-V market, where this open instruction set architecture (ISA) is gaining ground, and what are the biggest challenges in working with this technology.

SE: Where do you see the value in RISC-V? Is it for off-the-shelf processors or more customized components?

Prikryl: A few years ago, RISC-V was used mainly for embedded applications. Our customers were cautious, but they did realize the value of RISC-V because of its open ISA and the freedom to customize. About 18 months ago, we started to hear more questions about Linux-capable cores, which are much more complex. We’re also now seeing a lot more activity around AI cores. If you look at the European Processor Initiative, they’re used for co-processing, especially for vector processing, and it won’t stop there. I believe you also will see Android ported to RISC-V, as well, but it’s going to take some time. If you look at the RISC-V community, it started with small embedded cores. It has moved up to cores that are Linux-capable, and it is moving to very complex accelerators for vectors in multiprocessor systems. It won’t stop there either. Whenever you need a processor, you will be able to use RISC-V.

SE: AI really opened up a whole new world for RISC-V, right? Everything is in a constant state of change and there are a lot of customized applications.

Prikryl: Exactly, and the RISC-V ISA was designed to be extendable. In the case of AI, this is a good fit. Several different kinds of engines have been built and will be built in the future.

SE: Another market that has opened up for AI is China, because of the trade restrictions. As a result, China began developing a separate supply chain. What does that do for RISC-V?

Prikryl: Thanks to RISC-V’s open ISA and micro-architectural implementations being unrestricted, you see a lot of Chinese start-ups, big companies and open-source companies that have designed or are designing RISC-V processors from scratch in China. With RISC-V, we see a lot of traction at the universities, as well, AI is one of the leading applications areas for RISC-V.

SE: RISC-V potentially can be used for chiplets. How do you see this unfolding?

Prikryl: The concept is good, and it’s another opportunity for RISC-V. This is quite new. We haven’t seen that much activity around this yet. It probably will happen, but it’s hard to say when.

SE: Where else are you seeing big opportunities? What, how does this break down for you in terms of markets?

Prikryl: China is really active right now. In fact, it is the most active territory at the moment. With RISC-V, we see a lot of traction at the universities and in the companies. Pretty much every company has some kind of RISC-V strategy. Either they have adopted RISC-V already, or plan to do that quite soon. The next one from a geographical point of view is North America. The U.S. is quite active. You can see startups working with RISC-V in AI domains because you need to have some kind of customization, and RISC-V is very well positioned for that. Europe is also strong, especially in the universities. And last but not least, there is activity in places like Israel and Japan, although not as much as in China or America.

SE: What market segments are using RISC-V?

Prikryl: So far we’ve had a lot of interest in some segments, including image sensors, video processors, audio processing, AI/ML, and DSP for modems and wireless communications. It won’t just be one vertical market. It will be quite broad. So whenever you need some compute power — whether it’s a tiny MCU or a big vector machine — you can use RISC-V. We are not focused on any particular vertical, as we try to be as wide as possible. And thanks to the methodology that we are using, we can do that. Our processors are not necessarily tied to any specific domain.

SE: Are you finding that people are testing things out with RISC-V and then moving to different processors? Or are they staying with RISC-V?

Prikryl: We have an evaluation program, and it’s quite obvious that customers are testing not only our RISC-V, but also other vendors’ RISC-V, and other processor architectures. In some cases they realize that other processor architectures have some benefits that RISC-V doesn’t yet have. On the other hand, quite a few customers also realize that there are benefits in the case of RISC-V. I don’t think RISC-V will push other architectures completely away. The other architectures will be there, for sure, in the future. But RISC-V will take some of their market share.

SE: Also, more designs are becoming heterogeneous. So you may have an Arm core next to a RISC-V core, right?

Prikryl: The European Processor Initiative’s design is exactly as you mentioned. They have an Arm core as the main application processor, and then they have RISC-V accelerators. It’s a heterogeneous system. You only want to have RISC-V in a place where it makes sense — for example, because of the vector extensions. There can be other processors that are more tuned for certain applications, like CEVA for DSP. I don’t think we will end up with only RISC-V processors, but we will see RISC-V in many places.

SE: Are you finding opportunities in new markets like 5G and some automotive, as well? Are they starting to look at RISC-V?

Prikryl: Yes, and we have several leads in the automotive market. People have started asking questions about RISC-V, but it doesn’t mean they will put RISC-V into automotive now. They are investigating what they can do in a couple years. Automotive is slow to adopt new technology, and it will take some time before we see production devices. But companies that are involved in automotive have started asking what we can do and whether we can collaborate to make it happen in the next couple of years.

SE: So let’s dig into the some of the technology here and take a look under under the covers. How does Codasip approach the market with RISC-V, and what do you add to the code base?

Prikryl: Codasip started as an EDA company with tools for a processor design. Using these tools, you can design not only RISC-V, but any architecture you want. But in early 2015, when RISC-V started to become something real, we seized the opportunity and we started working on an implementation of a RISC-V core. We had the first version that year, and since then we’ve created a family of RISC-V compliant processors starting from small, power-efficient microcontrollers, and nowadays we are working on Linux-capable multi-core processors.

SE: That was for IoT devices, right?

Prikryl: Yes, that’s where we started. From there we created a processor that’s useful for really high-throughput, high-frequency, AI/machine learning types of things. After that, we started to see requests for Linux, so we created a Linux-capable core, and now we are moving to multiprocessor systems and also to big vectors. Other vendors like Andes and SiFive have done similar things. They also are marching from a small MCU up to bigger ones. What makes us different is that if you need to add special IP, you can do that with the EDA methodology we have behind it. Every IP that we have is described or designed with our EDA tool. If a customer needs to change either the ISA — for instance if you want to accelerate some computation — then the customer can add certain instructions to that extension by themselves because they have tools to do it. They can easily add key differentiation, not only on the ISA level, but also at the microarchitectural level. If you need to add some security capability or some microarchitecture tweaks, you can do that, as well. We are not limiting customization on the ISA. You can do pretty much anything you want with the design. And this is exactly what our customers like. They can take the baseline BK core, for instance, hook it together with some AI engine, and then develop a very good solution for AI. Or they can take the entry-level BK3, limit it to the bare minimum, and add a couple of special instructions to control something in the design. Also they can have really optimal solution from a power or code density point of view. So the combination of a vanilla, off-the-shelf, core plus the option of doing some customization is unique.

SE: EDA is an interesting starting point because it allows you to understand how to build, verify and test these devices. Tools that are really customized for RISC-V are in short supply.

Prikryl: Yes, and testing and verification are very important. We need to be sure that we deliver fully verified cores. Thanks to the EDA technology, we also have the ability to verify the extensions and make sure that you don’t break anything. For example, there is a generator that actually generates the UVM environment, which can be operated by the user to check that everything is working properly. You can do the customization, but you also have a framework or methodology to test and verify that everything’s fine.

SE: What’s unique about verifying a RISC-V core versus, say, an ARM core?

Prikryl: Every processor design needs to have a comprehensive functional verification plan, regardless of the ISA. Each of the RISC-V vendors has a different approach on how to implement the ISA, but you need to verify everything. For example, is the fetch unit working correctly?

SE: If you’re working with an Arm core, though, you pretty much know that it’s going to work. With a RISC-V core, you may be doing a lot of customization. So you do need to make sure that it will work, right?

Prikryl: Yes. If you take a standard core, it’s basically the same type of verification. But if you are adding customization into it, then you need a framework that helps you check that everything’s fine and nothing’s broken. We have a tool set that supports that, and we use it in-house, as well.

SE: When you do this level of customization, what changes in the design-through-verification flow? You’ve made changes that are different than what is the standard core. Now, how do you go about making sure that they all work?

Prikryl: First of all, it has to be compliant to RISC-V. It needs to pass the compliance test suite. Then, if you have custom extensions, you need have direct tests and/or generate random sequences to verify the extensions.

SE: Typically, AI designs are in motion. They optimize over time, the algorithms change, and with RISC-V, the ISA is updated. How does all of this impact design?

Prikryl: We can do changes quite quickly. Last year, we were working with a U.S.-based company to make code smaller and denser, because the standard C extension is not as good as it should be. We looked at the ISA and came up with new options for compact instructions. We did the first design space exploration in two days, and we got good results and presented it at the RISC-V Summit. The design space exploration is important in this, especially for AI where everything is moving, like you mentioned. You need to be able to do design exploration in a short period of time. That allows us to follow the moving target quite efficiently.

Related Stories
RISC-V Knowledge Center
Top stories, blogs, white papers on RISC-V
RISC-V Gaining Traction
Experts at the Table: Extensible instruction-set architecture is drawing attention from across the industry and supply chain.



Leave a Reply


(Note: This name will be displayed publicly)