tag: heterogeneous integration

Impact Of Increased IC Performance On Memory
By Ed Sperling - 30 Mar, 2023 - Comments: 0

Increasing performance in advanced semiconductors is becoming more difficult as chips become more complex. There are more physical effects to contend with, different use cases, and challenges in making memory go faster. In addition, aging effects that once were ignored are now becoming critical concerns. Steven Woo, fellow and distinguished inventor at Rambus, talks about different factors that... » read more

Room-Temperature Metal Bonding Technology That Facilitates The Fabrication of 3D-ICs & 3D Integration With Heterogeneous Devices
By Technical Paper Link - 19 Mar, 2023 - Comments: 0

A technical paper titled "Room-Temperature Direct Cu Semi-Additive Plating (SAP) Bonding for Chip-on-Wafer 3D Heterogenous Integration With μLED" was published by researchers at Tohoku University in Japan. Abstract: "This letter describes a direct Cu bonding technology to there-dimensionally integrate heterogeneous dielets based on a chip-on-wafer configuration. 100- μm -cubed blue μ LED... » read more

Test Challenges Mount As Demands For Reliability Increase
By Anne Meixner - 07 Mar, 2023 - Comments: 0

An emphasis of improving semiconductor quality is beginning to spread well beyond just data centers and automotive applications, where ICs play a role in mission- and safety-critical applications. But this focus on improved reliability is ratcheting up pressure throughout the test community, from lab to fab and into the field, in products where transistor density continues to grow — and wh... » read more

How To Build Resilience Into Chips
By Ed Sperling and Ann Mutschler - 27 Feb, 2023 - Comments: 0

Disaggregating chips into specialized processors, memories, and architectures is becoming necessary for continued improvements in performance and power, but it's also contributing to unusual and often unpredictable errors in hardware that are extremely difficult to find. The sources of those errors can include anything from timing errors in a particular sequence, to gaps in bonds between chi... » read more

Week In Review: Semiconductor Manufacturing, Test
By Karen Heyman - 03 Feb, 2023 - Comments: 0

Imec released its semiconductor roadmap, which calls for doubling compute power every six months to handle the data explosion and new data-intensive problems. Imec named five walls (scaling, memory, power, sustainability, cost) that need to be dismantled. The roadmap (below) stretches from 7nm to 0.2nm (2 angstroms) by 2036, and includes four generations of gate-all-around FETs followed by thre... » read more

Unknowns And Challenges In Advanced Packaging
By Ed Sperling - 19 Jan, 2023 - Comments: 0

Dick Otte, CEO of Promex Industries, sat down with Semiconductor Engineering to talk about unknowns in material properties, the impact on bonding, and why environmental factors are so important in complex heterogeneous packages. What follows are excerpts of that conversation. SE: Companies have been designing heterogeneous chips to take advantage of specific applications or use cases, but th... » read more

The Path To Known Good Interconnects
By Laura Peters - 19 Jan, 2023 - Comments: 1

Chiplets and heterogenous integration (HI) provide a compelling way to continue delivering improvements in performance, power, area, and cost (PPAC) as Moore’s Law slows, but choosing the best way to connect these devices so they behave in consistent and predictable ways is becoming a challenge as the number of options continues to grow. More possibilities also bring more potential interac... » read more

Metrology Options Increase As Device Needs Shift
By Laura Peters - 10 Jan, 2023 - Comments: 1

Semiconductor fabs are taking an ‘all hands on deck’ approach to solving tough metrology and yield management challenges, combining tools, processes, and other technologies as the chip industry transitions to nanosheet transistors on the front end and heterogenous integration on the back end. Optical and e-beam tools are being extended, while X-ray inspection is being added on a case-by-... » read more

Designing For Multiple Die
By Ann Mutschler - 21 Dec, 2022 - Comments: 1

Integrating multiple die or chiplets into a package is proving to be very different than putting them on the same die, where everything is developed at the same node using the same foundry process. As designs become more heterogeneous and disaggregated, they need to be modeled, properly floor-planned, verified, and debugged in the context of a system, rather than as individual components. Typi... » read more

Adapting To Broad Shifts Essential In 2022
By Brian Bailey - 21 Dec, 2022 - Comments: 0

Change creates opportunity, but not every company is able to respond quickly enough to take advantage of those opportunities. Others may respond too quickly, before they properly understand the implications. At the start of a typical year, optimism is in plentiful supply. Any positive trend is seen as continuing, and any negative is seen as turning around. Normally the later in the year that... » read more

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