tag: IBM

Building A Better CMOS FET
By Barry Pangrle - 21 Jul, 2011 - Comments: 0

By Barry Pangrle SEMICON West was held last week in San Francisco and I had the opportunity to attend the Emerging Architectures session. Serge Biesemans, vice president of process technology at Imec, gave a nice overview presentation on FinFETs. From a power and performance standpoint, we’ve seen some early pre-production information released from Intel that I briefly discussed here. Serge�... » read more

New Wii U™ on SOI
By Various Writers - 08 Jul, 2011 - Comments: 0

By Adele Hars If you've followed the industry buzz in recent weeks, you've seen the news: the CPU for Nintendo's upcoming (and very cool) Wii U is on IBM's 45nm SOI. IBM's been fabbing chips for Nintendo for over a decade, and first moved the company's CPUs to SOI in 2006, at 90nm. The Wii U, which got its debut at the recent E3 show, will hit the shelves in 2012. The Wii U combines m... » read more

The Tao Of Software
By Ed Sperling - 16 Jun, 2011 - Comments: 0

By Ed Sperling and Pallab Chatterjee As software teams continue to race past hardware teams in numbers of engineers, hours spent on designs and NRE budgets, companies are beginning to question whether there needs to be a fundamental shift in priorities and strategy. The problem is that it takes far too long to write and debug the software and to get it working on the hardware, even with vir... » read more

Tri-Gate’s Fallout
By Ed Sperling - 26 May, 2011 - Comments: 0

By David Lammers Intel Corp. dropped a rock into the pond of transistor technology when it announced its 22nm tri-gate technology in San Francisco earlier this month. The ripples continue to move out from that event, with impacts on IDMs, foundries, and fabless semiconductor companies being closely studied. Now that Intel has come out of the closet with its tri-gate technology, “the found... » read more

Waiting for Porous Low-k
By Katherine Derbyshire - 12 May, 2011 - Comments: 0

I'm working on a longer article on low-k dielectric integration, but in the meantime I wanted to pass along an observation from Joubert Olivier of LTM-CNRS, in his presentation at the Materials Research Society Spring Meeting. Asked about the prospects for low-k integration, he reminded the audience that even if an integration scheme is able to achieve good selectivity between the hard mask ... » read more

The SOI Papers at ISSCC 2011
By Various Writers - 15 Mar, 2011 - Comments: 0

By Adele Hars The International Solid-State Circuits Conference — better known as ISSCC — is of course where the big guns show us their big advances at the chip level. At the most recent conference, held a few weeks ago in San Francisco, advances that leveraged SOI were once again at the forefront. As always, performance gains generate plenty of buzz. But the SOI papers were also nota... » read more

Material Effects: Trading Performance For Power
By Ed Sperling - 13 Jan, 2011 - Comments: 0

By Ann Steffora Mutschler Power impacts everything, even when it comes to semiconductor manufacturing materials. While bulk CMOS technology still reigns supreme, there are a number of advanced materials being suggested as replacements when it runs out of steam at around 15nm, including silicon on insulator (SOI)—particularly in combination with FinFET multigate structures on SOI—silicon ge... » read more

Beyond 22nm
By Ed Sperling - 15 Dec, 2010 - Comments: 0

Gary Patton, VP at IBM's semiconductor R&D Center, talks with System-Level Design about the challenges of developing chips all the way down to 15nm. [youtube vid=2wTj3EvRIRw]   » read more

The Growing Legacy Of Moore’s Law
By Ed Sperling - 02 Dec, 2010 - Comments: 0

By Ed Sperling Moore’s Law has defined semiconductor design since it was introduced in 1965, but increasingly it also has begun defining the manufacturing equipment, the cooling needed for end devices, and both the heat and performance of systems. In the equipment sector the big problem has been the delay in rolling out extreme ultraviolet (EUV). Moore’s Law will require tighter spacing... » read more

Getting Ready For 15nm
By Ed Sperling - 07 Oct, 2010 - Comments: 0

By David Lammers The trends towards vertical transistors, non-silicon channel materials, and resistive RAMs promise to hold center stage at the 2010 IEEE International Electron Devices Meeting (IEDM), set to begin Dec. 6 in San Francisco, Calif. (www.ieee-iedm.org) Taiwan Semiconductor Manufacturing Co. (TSMC, Hsinchu, Taiwan) will present a 22/20nm technology platform based on a FinFET arc... » read more

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