tag: III-V materials

One-On-One: Thomas Caulfield
By Mark LaPedus - 21 May, 2015 - Comments: 0

Semiconductor Engineering sat down to talk about fabs, process technology and the equipment industry with Thomas Caulfield, senior vice president and general manager of Fab 8 at [getentity id="22819" comment="GlobalFoundries"]. Located in Saratoga County, N.Y., Fab 8 is GlobalFoundries’ most advanced 300mm wafer fab. What follows are excerpts of that discussion. SE: Last year, GlobalFoundr... » read more

Still Waiting For III-V Chips
By Mark LaPedus - 19 Feb, 2015 - Comments: 0

For years, chipmakers have been searching for an alternative material to replace traditional silicon in the channel for advanced CMOS devices at 7nm and beyond. There’s a good reason, too: At 7nm, silicon will likely run out of steam in the channel. Until recently, chipmakers were counting on III-V materials for the channels, at least for NFET. Compared to silicon, III-V materials provide ... » read more

What Happened To GaN And SiC?
By Mark LaPedus - 03 Feb, 2015 - Comments: 6

About five years ago, some chipmakers claimed that traditional silicon-based power MOSFETs had hit the wall, prompting the need for a new power transistor technology. At the time, some thought that two wide-bandgap technologies—gallium nitride (GaN) on silicon and silicon carbide (SiC) MOSFETs—would displace the ubiquitous power MOSFET. In addition, GaN and SiC were supposed to pose a t... » read more

Next Channel Materials?
By Mark LaPedus - 22 Jan, 2015 - Comments: 0

Chipmakers are making a giant leap from planar transistors to [getkc id="185" kc_name="finFETs"]. Initially, [getentity id="22846" e_name="Intel"] moved into finFET production at 22nm and is now ramping up its second-generation finFETs at 14nm. And the other foundries will enter the finFET fray at 16nm/14nm. So what’s next? Chipmakers will likely extend the finFET architecture to both 10nm... » read more

One-On-One: Aaron Thean
By Mark LaPedus - 22 Jan, 2015 - Comments: 0

Semiconductor Engineering sat down to discuss process technology, transistor trends and other topics with Aaron Thean, vice president of process technologies and director of the logic devices R&D program at Imec. SE: Chipmakers are ramping up the 16nm/14nm logic node, with 10nm and 7nm in R&D. What’s the current timeline for 10nm and 7nm? Thean: 10nm is on its way. We will see r... » read more

And the Winner is…
By Brian Bailey - 18 Dec, 2014 - Comments: 0

Semiconductor Engineering now has its first full year under its belt, and I have to say it has been an incredible year. Not only did we exceed a million page views in our first year, but we also got started on the Knowledge Center, an endeavor the likes of which has never been attempted in our industry. It is still very young and has a lot of growing up to do, but it is a wonderful start. We wo... » read more

Transistor Options Narrow For 7nm
By Mark LaPedus - 13 Nov, 2014 - Comments: 0

Chipmakers are currently ramping up silicon-based finFETs at the 16nm/14nm node, with plans to scale the same technology to 10nm. Now, the industry is focusing on the transistor options for 7nm and beyond. At one time, the leading contenders involved several next-generation transistor types. At present, the industry is narrowing down the options and one technology is taking a surprising lea... » read more

Will There Be A DDR5?
By Ed Sperling - 10 Oct, 2014 - Comments: 1

DDR4 rollouts have begun. And in the DRAM world that begs the question, 'What comes next?' The answer isn't so obvious. While there have been suggestions inside of JEDEC — the Joint Electron Device Engineering Council, which has overseen the standards for double-data-rate synchronous DRAM — to develop a DDR5 standard, it's not the only solution being considered. And in the minds of some... » read more

Why Investments At Advanced Nodes Matter
By Ed Sperling - 18 Sep, 2014 - Comments: 0

Despite all the talk about rising costs of development, uncertainties about lithography and talk about the death of Moore’s Law, a record number of companies are developing chips at 16nm/14nm. That may sound surprising, but asking why that’s happening is probably the wrong question. The really critical question is what they’re going to do with those chips. What’s become quite evident... » read more

One-On-One: Mark Bohr
By Mark LaPedus - 18 Sep, 2014 - Comments: 1

Semiconductor Engineering sat down to discuss process technology, transistor trends, chip-packaging and other topics with Mark Bohr, a senior fellow and director of process architecture and integration at Intel. SE: Intel recently introduced chips based on its new 14nm process. Can you briefly describe the 14nm process? Bohr: It’s our second-generation, tri-gate technology. So it has al... » read more

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