Big Changes Ahead For Photomask Technology


The move to curvilinear shapes on photomasks is gaining steam after years of promise as a way of improving yield, lowering defectivity, and reducing wasted space on a die — all of which are essential for both continued scaling and improved reliability in semiconductors. Interest in this approach ran high at this year's SPIE Photomask Technology + EUV Lithography Conference. Put simply, cur... » read more

Chip Industry Week In Review


By Jesse Allen, Liz Allan, and Gregory Haley A potential government shutdown beginning in November would be "massively disruptive" for the Commerce Department as it continues to disburse critical funding featured in the CHIPS Act to boost semiconductor research and development in the U.S., according to Secretary Gina Raimondo. Global semiconductor industry sales totaled $44 billion in Aug... » read more

Building Better Bridges In Advanced Packaging


The increasing challenges and rising cost of logic scaling, along with demands for an increasing number of features, are pushing more companies into advanced packaging. And while that opens up a slew of new options, it also is causing widespread confusion over what works best for different processes and technologies. At its core, advanced packaging depends on reliable interconnects, well-def... » read more

Technical Paper Roundup: Sept 5


New technical papers added to Semiconductor Engineering’s library this week. [table id=132 /] (more…) » read more

Investigating The Ru/Ta Bilayer As An Alternative EUV Absorber To Mitigate Mask 3D Effects


A technical paper titled “Ru/Ta bilayer approach to EUV mask absorbers: Experimental patterning and simulated imaging perspective” was published by researchers at KU Leuven and imec. Abstract: "The optical properties and geometry of EUV mask absorbers play an essential role in determining the imaging performance of a mask in EUV lithography. Imaging metrics, including Normalized Imag... » read more

Formal Processor Model Providing Provably Secure Speculation For The Constant-Time Policy


A new technical paper titled "ProSpeCT: Provably Secure Speculation for the Constant-Time Policy" was published by researchers at imec-DistriNet, KU Leuven, CEA, and INRIA. This paper was included at the recent 32nd USENIX Security Symposium. Abstract: "We propose ProSpeCT, a generic formal processor model providing provably secure speculation for the constant-time policy. For constant-tim... » read more

Week In Review: Automotive, Security and Pervasive Computing


The AAA Foundation for Traffic Safety estimates that between 2021 and 2050, ADAS technologies currently available to U.S. will prevent "approximately 37 million crashes, 14 million injuries, and nearly 250,000 deaths, which would represent 16% of crashes and injuries, and 22% of deaths that would otherwise occur on U.S. roads without these technologies," according to a new report. Governmen... » read more

Directed Self-Assembly Finds Its Footing


Ten years ago, when the industry was struggling to deliver EUV lithography, directed self-assembly (DSA) roared to the forefront of research and development for virtually every manufacturer determined to extend the limits of 193i. It was the hot topic at of the 2012 SPIE Advanced Lithography Conference, with one attendee from Applied Materials comparing its potential to disrupt the industry to ... » read more

MRAM Getting More Attention At Smallest Nodes


Magneto-resistive RAM (MRAM) appears to be gaining traction at the most advanced nodes, in part because of recent improvements in the memory itself and in part because new markets require solutions for which MRAM may be uniquely qualified. There are still plenty of skeptics when it comes to MRAM, and lots of potential competitors. That has limited MRAM to a niche role over the past couple de... » read more

Navigating the Metrology Maze For GAA FETs


The chip industry is pushing the boundaries of innovation with the evolution of finFETs to gate-all-around (GAA) nanosheet transistors at the 3nm node and beyond, but it also is adding significant new metrology challenges. GAA represents a significant advancement in transistor architecture, where the gate material fully encompasses the nanosheet channel. This approach allows for the vertical... » read more

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