Sidestepping Lithography In Chip Manufacturing


Rising lithography costs, shrinking feature sizes, and the need for an alternative to copper are collectively spurring new interest in area-selective deposition. An extension of atomic layer deposition, ASD seeks to build circuit features from the bottom up, without relying on lithography. Lithography will remain a critical tool for the foreseeable future. But it has long been the most expen... » read more

Proof-of-Concept On-Chip Flow Cytometer Using Integrated Photonics (imec, Sarcura)


A new technical paper titled "On-chip flow cytometer using integrated photonics for the detection of human leukocytes" was published by researchers at imec and Sarcura GmbH. Abstract "Differentiation between leukocyte subtypes like monocytes and lymphocytes is essential for cell therapy and research applications. To guarantee the cost-effective delivery of functional cells in cell therapies... » read more

Chip Industry Technical Paper Roundup: May 21


New technical papers added to Semiconductor Engineering’s library this week. [table id=227 /] More ReadingTechnical Paper Library home » read more

Demonstrating The Feasibility Of The Foundry Model For Flexible Thin-Film Electronics 


A technical paper titled “Multi-project wafers for flexible thin-film electronics by independent foundries” was published by researchers at KU Leuven and imec. Abstract: "Flexible and large-area electronics rely on thin-film transistors (TFTs) to make displays, large-area image sensors, microprocessors, wearable healthcare patches, digital microfluidics and more. Although silicon-based co... » read more

Dealing With AI/ML Uncertainty


Despite their widespread popularity, large language models (LLMs) have several well-known design issues, the most notorious being hallucinations, in which an LLM tries to pass off its statistics-based concoctions as real-world facts. Hallucinations are examples of a fundamental, underlying issue with LLMs. The inner workings of LLMs, as well as other deep neural nets (DNNs), are only partly kno... » read more

Chip Industry Technical Paper Roundup: April 23


New technical papers recently added to Semiconductor Engineering’s library. [table id=216 /] Find last week’s technical paper additions here. » read more

Deep Learning (DL) Applications In Photomask To Wafer Semiconductor Manufacturing


How Advantest Corporation, ASML, Fraunhofer, imec, Siemens EDA and others are using deep learning in semiconductor manufacturing. Click here to read more. » read more

Chip Industry Week In Review


Applied Materials may scale back or cancel its $4 billion new Silicon Valley R&D facility in light of the U.S. government's recent announcement to reduce funding for construction, modernization, or expansion of semiconductor research and development (R&D) facilities in the United States, according to the San Francisco Chronicle. TSMC could receive up to $6.6 billion in direct funding... » read more

High-NA EUVL: Automated Defect Inspection Based on SEMI-SuperYOLO-NAS


A new technical paper titled "Towards Improved Semiconductor Defect Inspection for high-NA EUVL based on SEMI-SuperYOLO-NAS" was published by researchers at KU Leuven, imec, Ghent University, and SCREEN SPE. Abstract "Due to potential pitch reduction, the semiconductor industry is adopting High-NA EUVL technology. However, its low depth of focus presents challenges for High Volume Manufac... » read more

Startup Funding: March 2024


The challenge of moving data from place to place is increasingly a key concern for chip and system designers, and investors are taking note. Numerous startups developing interconnect technologies received significant backing in March, with approaches spanning chiplet-enabling PHYs, photonic fabrics for disaggregated compute and memory, and telecom transceiver modules. Several new startups la... » read more

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