Chip Industry Week in Review


Samsung and SK hynix joined OpenAI's Stargate initiative to ensure there will be enough memory chips to meet the needs of AI data centers. The goal is to produce up to 900,000 DRAM wafer starts per month. OpenAI also inked agreements to explore the development of next-gen data centers in Korea. Axcelis Technologies (ion implantation systems) will merge with Veeco Instruments (compound semic... » read more

Chip Industry Week In Review


U.S. Trade Representative Jamieson Greer warned Southeast Asian semiconductor manufacturers that they must shift production to the U.S. or face new punitive tariffs, reports the South China Morning Post. President Trump previously floated a 100% tariff on imported chips. Malaysia and other regional economies are offering large concessions and promises of U.S. goods purchases in hopes of securin... » read more

Mitigating Warpage In Multi-Chiplet Systems


Warpage of dies, redistribution layers, and interposers is a growing problem in multi-chiplet packages, and it can have a dramatic impact on the behavior and reliability of these devices. Multiple factors contribute to warpage, including larger chip sizes, severe thinning of the silicon substrate, temporary bonding and debonding processes, and scaling of bump pitch and size. Each of these ca... » read more

Chip Industry Week in Review


Amkor, TSMC, and Cadence partnered with Tesoro VC, which will serve as the lead operator of a new Global AI + Semiconductor Startup Hub and a Global Design Center in Phoenix, Arizona, aimed at chip innovation, startup growth, and advanced manufacturing. Nvidia will invest $5 billion in Intel common stock at a purchase price of $23.28 per share and the companies will collaborate on AI infrastru... » read more

Scaling Memory With Molybdenum


Molybdenum is looking increasingly promising as a replacement for a variety of metals commonly used in semiconductor manufacturing today, especially at leading-edge nodes. One by one, chipmakers are crossing metals off the list at advanced nodes. While ruthenium liners are nearly ready for production, the metal is not ready to replace copper in highly scaled interconnects. Ruthenium is very ... » read more

Chip Industry Week in Review


The U.S. is considering annual approvals for Samsung and SK hynix to export chipmaking tools and materials to their factories in China, replacing perpetual waivers granted under the validated end user system, reports Bloomberg. The proposal, presented by the U.S. Commerce Department to South Korean officials, would require the companies to reapply each year for specific quantities of restricted... » read more

Chip Industry Technical Paper Roundup: Sept 8


New technical papers recently added to Semiconductor Engineering’s library: [table id=471 /] Find more semiconductor research papers here. » read more

Cross-Node Scaling Potential of SOT-MRAM for Last-Level Caches (imec)


A new technical paper titled "SOT-MRAM Bitcell Scaling with BEOL Read Selectors: A DTCO Study" was published by researchers at imec, Leuven, and 3001 Belgium. Abstract "This work explores the cross-node scaling potential of SOT-MRAM for last-level caches (LLCs) under heterogeneous system scaling paradigm. We perform extensive Design-Technology Co-Optimization (DTCO) exercises to evaluate th... » read more

Chip Industry Technical Paper Roundup: August 26


New technical papers recently added to Semiconductor Engineering’s library: [table id=467 /] Find more semiconductor research papers here. » read more

How Semiconductor Fabs Use Water


Water — lots of it — is a critical enabler for advanced chip architectures, lithography, and back-end packaging. It feeds the ultra-pure water loops that touch every wafer, sluicing heat out of tools that run hotter at each node, and carrying spent chemistries to treatment. The natural reaction to reports that fabs “use millions of gallons of water” is concern, but the engineering re... » read more

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