Ultra Ethernet overview; wire-friendly domain-specific processor design; multi-chiplet PIM architectures; photonic fabrics; architecting long-context LLM; high-yield lithography protocol; reconfigurable CNT FeFET.
New technical papers recently added to Semiconductor Engineering’s library:
| Technical Paper | Research Organizations |
|---|---|
| Ultra Ethernet’s Design Principles and Architectural Innovations | ETH Zurich, Broadcom, Hewlett Packard Enterprise, OpenAI, Intel, Microsoft, AMD, Cisco |
| Physical Design Exploration of a Wire-Friendly Domain-Specific Processor for Angstrom-Era Nodes | Politecnico di Torino, EPFL, National Technical University of Athens, imec |
| THERMOS: Thermally-Aware Multi-Objective Scheduling of AI Workloads on Heterogeneous Multi-Chiplet PIM Architectures | University of Wisconsin–Madison, Washington State University |
| Morphlux: Programmable chip-to-chip photonic fabrics in multi-accelerator servers for ML | Cornell University and Lightmatter |
| High-yield photolithography protocol to pattern metallic electrodes on 2D materials without adhesive metallic layers | KAUST and National University of Singapore |
| Architecting Long-Context LLM Acceleration with Packing-Prefetch Scheduler and Ultra-Large Capacity On-Chip Memories | Georgia Institute of Technology, Samsung |
| Reconfigurable single-walled carbon nanotube ferroelectric field-effect transistors | University of Pennsylvania, Yonsei University, Kookmin University, SKKU and Peking University |
Find more semiconductor research papers here.
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