Future of memory; leveraging 3D for HW security; LLMs for EDA; high-level synthesis; optimizing power in multi-core systems; processing-in-memory architectures; wafer-scale heterogeneous integration PICs; imec’s SOT-MRAM bitcell scaling; AI deployment systems, operation cybersecurity.
New technical papers recently added to Semiconductor Engineering’s library:
| Technical Paper | Research Organizations |
|---|---|
| The Future of Memory: Limits and Opportunities | Stanford University et al. |
| Leveraging 3D Technologies for Hardware Security: Opportunities and Challenges | UCSB, Columbia Univ. |
| Large Language Models (LLMs) for Electronic Design Automation (EDA) | TU Munich, Univ. of Stuttgart, NYU, Univ. of Siegen |
| Simulating Hardware with C Speed and RTL Accuracy for High-Level Synthesis Designs | Georgia Tech |
| Balancing Power and Performance With Task Dependencies in Multi-Core Systems | TU Dresden |
| New Tools, Programming Models, and System Support for Processing-in-Memory Architectures | ETH Zurich |
| Heterogeneously integrated lithium tantalate-on-silicon nitride modulators for high-speed communications | EPFL, Chinese Academy of Sciences, IPQ, KIT |
| SOT-MRAM Bitcell Scaling with BEOL Read Selectors: A DTCO Study | imec |
| Surveying the Operational Cybersecurity and Supply Chain Threat Landscape when Developing and Deploying AI Systems | Sandia National Labs |
Find more semiconductor research papers here.
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