Chip Industry Week In Review

By The SE Staff - 22 Aug, 2025 - Comments: 0

The EU’s tariffs on semiconductors will not exceed 15%, according to Trump’s latest trade deal. In addition, the EU committed to purchasing at least $40 billion worth of U.S. AI chips as well as other investments. [FAQ is here.] Lifelines for Intel: Intel inked a deal to sell the U.S. government a 10% non-voting equity stake in its business, worth $8.9 billion. The stake will be fun... » read more

Manufacturing At The Limits

By Gregory Haley - 21 Aug, 2025 - Comments: 2

Hybrid bonding has been in production for several years, with mature flows capable of delivering robust yields using 10µm interconnects. At that scale, processes can tolerate hundreds of nanometers of overlay variation, modest differences in wafer bow, and particle sizes rivaling the interconnect height without catastrophic impact. Hybrid bonding is compatible with optical metrology, existing ... » read more

The End Of Copper Interconnects?

By Katherine Derbyshire - 21 Aug, 2025 - Comments: 0

After nearly three decades, the era of copper interconnects may be coming to an end. Sort of. At interconnect CDs below 10nm, copper is no longer the best metallization choice. Yet it remains unsurpassed for larger features. The most serious challenge to continued copper scaling is the metal’s dramatic increase in resistivity at dimensions below its relatively large (40nm) mean free path l... » read more

Wire-Friendly Domain-Specific Processor for Angstrom-Era Nodes with High Core Density (Politecnico di Torino, imec et al.)

By Technical Paper Link - 19 Aug, 2025 - Comments: 0

A new technical paper titled "Physical Design Exploration of a Wire-Friendly Domain-Specific Processor for Angstrom-Era Nodes" was published by researchers at Politecnico di Torino, EPFL, National Technical University of Athens and imec. Abstract "This paper presents the physical design exploration of a domain-specific processor (DSIP) architecture targeted at machine learning (ML), address... » read more

Chip Industry Week in Review

By The SE Staff - 15 Aug, 2025 - Comments: 0

Lines are blurring between government and industry: On the heels of last week's resignation demand, Intel CEO Lip-Bu Tan met with President Trump on Monday, with the President later saying, "The meeting was a very interesting one. His success and rise is an amazing story." Now, Bloomberg reports the Trump administration is in talks with Intel for the U.S. government to take a stake in th... » read more

Metrology Under Pressure: Detecting Defects in Fine-Pitch Hybrid Bonding

By Gregory Haley - 12 Aug, 2025 - Comments: 1

As advanced packaging pushes deeper into the sub-10µm realm, traditional inspection and metrology systems are being forced to evolve with it. Hybrid bonding, a critical enabler of vertical integration and 3D system performance, relies on exceptionally tight alignment and defect-free bonding surfaces. But as interconnect pitch shrinks, even nanometer-scale variations in height, tilt, or cont... » read more

Chip Industry Technical Paper Roundup: August 11

By Emma Riverso - 11 Aug, 2025 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library: [table id=463 /] Find more semiconductor research papers here. » read more

Epitaxial Growth Of Up To 120 Si/SiGe Bilayers In View of 3D DRAM Applications (imec, Ghent Univ.)

By Technical Paper Link - 05 Aug, 2025 - Comments: 0

A new technical paper titled "Epitaxial growth of up to 120× {Si0.8Ge0.2/Si} bilayers in view of three dimensional dynamic random access memory applications" was published by researchers at imec and Ghent University. Abstract "Epitaxially grown Si/Si1−xGex multi-stacks with ≥100 bilayers (≥200 sublayers) are being considered for three dimensionally vertically stacked dynamic rando... » read more

Chip Industry Week in Review

By The SE Staff - 25 Jul, 2025 - Comments: 0

Intel reported flat year-over year revenue for Q2, exceeding Wall Street's pessimistic expectations. In a message to employees, CEO Lip-Bu Tan said the company will: Cut about 15% of its staff, ending the year with about 75,000 employees, down from a high of nearly 132,000 in 2022; Scrap projects in Poland and Germany, consolidate other sites in central America and Southeast Asia, and s... » read more

CMOS 2.0: Layered Logic For The Post-Nanosheet Era

By Gregory Haley - 24 Jul, 2025 - Comments: 0

The semiconductor industry has relied on a simple equation for more than five decades — shrink the transistor, pack more onto every wafer, and watch performance soar as costs plummet. While each new node delivered predictable gains in speed, power efficiency, and density, that formula is rapidly running out of steam. As transistors approach single-digit nanometer processes, manufacturing c... » read more

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tag: imec

Chip Industry Week In Review

Manufacturing At The Limits

The End Of Copper Interconnects?

Wire-Friendly Domain-Specific Processor for Angstrom-Era Nodes with High Core Density (Politecnico di Torino, imec et al.)

Chip Industry Week in Review

Metrology Under Pressure: Detecting Defects in Fine-Pitch Hybrid Bonding

Chip Industry Technical Paper Roundup: August 11

Epitaxial Growth Of Up To 120 Si/SiGe Bilayers In View of 3D DRAM Applications (imec, Ghent Univ.)

Chip Industry Week in Review

CMOS 2.0: Layered Logic For The Post-Nanosheet Era

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