Ruthenium plays a key role at advanced nodes, but it’s not a wholesale replacement.
After nearly three decades, the era of copper interconnects may be coming to an end. Sort of. At interconnect CDs below 10nm, copper is no longer the best metallization choice. Yet it remains unsurpassed for larger features.
The most serious challenge to continued copper scaling is the metal’s dramatic increase in resistivity at dimensions below its relatively large (40nm) mean free path length. When the line width is less than 10nm, electron scattering causes about a 10-fold increase in line resistance relative to the bulk material, according to Jun Hwan Moon, a Samsung materials scientist, and his colleagues.
Moreover, because copper requires a diffusion barrier, the actual copper wire is always smaller than the pattern on the photomask. Diffusion barriers are not effective unless they’re at least 3 to 4nm thick, meaning a 10nm line will only have 2 to 4nm of copper metal. [1]
The need for barrier layers also complicates the fabrication of very small features. There is no manufacturable copper etching process. Instead, even the narrowest lines are fabricated by etching lines in the dielectric, depositing the barrier and seed layers, then filling with copper. Effective barrier deposition requires uniform sidewall coverage combined with the ability to inhibit deposition in via bottoms. Effective copper deposition tunes the electroplating bath chemistry to ensure a bottom-up, void-free fill.
While selective deposition is an active research area, it’s clear that smaller dimensions leave less room for inhibitor molecules. Moon said the smaller lines mean increasing current density, while higher resistance leads to increased heating. Both factors increase the risk of electromigration.
So any alternative conductor needs to be what copper is not. It needs low resistance with a short mean free path, it needs to resist electromigration, and it should resist diffusion into SiO2 and SiOCH dielectrics. That’s where ruthenium comes in.
Ruthenium at the copper interface
Ruthenium first drew the attention of the semiconductor industry as a low-resistance alternative to the then-prevalent TaN diffusion barrier. It blocks copper diffusion as well as TaN, but the net resistance of a Ru-lined copper interconnect is lower. Ruthenium’s impressive properties caused researchers to look at it for more than just a liner.
As a primary conductor, ruthenium surpasses copper’s conductivity for line CDs of 17nm or less, and has excellent electromigration resistance. Also, unlike copper, ruthenium is relatively easy to etch, opening the door to more flexible process integration schemes. On the other hand, Moon said that ruthenium is difficult to deposit by electrodeposition and difficult to remove by CMP.
Ruthenium’s compatibility with copper is especially important because, as noted, copper almost certainly will remain the metal of choice for all the lines wider than 20nm. The interface between any alternative conductor and the copper wiring layers above it is critical to the overall success of the device.
Another Samsung group, in collaboration with imec, examined diffusion and intermixing at the interface between copper and ruthenium. Engineer Sunyoung Noh and his colleagues at Samsung presented their work at the IEEE International Interconnect Technology Conference (IITC) in June, in which they used a self-assembled monolayer (SAM) to prevent barrier layer deposition at the bottoms of vias. For sidewalls, they used either a cobalt-ruthenium bilayer or one of several cobalt layer thicknesses. Unsurprisingly, they found that reducing the barrier layer thickness reduced the overall line resistance. They also showed that copper did not intermix with ruthenium at the via bottoms. Even more important, by using a thin liner and eliminating the via bottom barrier the electromigration performance remained. [2]
Materials science of ruthenium
The size dependence of copper’s resistivity is especially inconvenient in vias. In ring oscillator simulations, Marleen H. van der Veen, nanointerconnects metallization specialist at imec, and her colleagues found that ruthenium vias (21nm pitch) combined with copper wires (24nm pitch) gave lower chain resistance than barrierless dual damascene ruthenium alone. They experimented with several CVD ruthenium precursors to optimize fill characteristics. In the end, a 1.5nm TiN liner passivated the dielectric and facilitated ruthenium adhesion. [3]
Interestingly, because ruthenium is more easily etched than copper, a single semidamascene structure can combine both additive and subtractive metallization processes. In this approach, vias etched into the blanket dielectric are filled with ruthenium. A blanket ruthenium film is deposited on top, then etched to create trenches that are subsequently filled with the dielectric. Because the metal is patterned, rather than the dielectric, this approach also greatly simplifies air-gap dielectric schemes.
Though these possibilities are intriguing, they depend on processes that can deposit and remove ruthenium consistently across millions of features on thousands of wafers. The industry is only starting to understand the relationships between ruthenium deposition conditions, crystal structure, and properties. For example, PVD ruthenium does not adhere well to SiO2, but using an adhesion layer reduces the effective width of the line. Researchers at Japan’s Keio University found that reducing deposition pressure produced a denser, lower-resistance film, but made adhesion worse. Good news may be coming as line-width scales down, though, because the same group found that reducing the film thickness improves adhesion.[4]
In diffusion barriers, Moon said the columnar grains that typically occur in sputtered ruthenium films can provide a pathway for copper diffusion. Instead, sputtering in a nitrogen atmosphere can help develop a more robust amorphous structure. Alloying ruthenium with tungsten or cobalt also can improve the barrier properties.
Using ruthenium as a primary conductor allows more flexible deposition methods. For instance, CVD and ALD processes typically require temperatures around 300°C. Instead, Takanobu Hamamura, researcher at Kansai University, and his colleagues investigated the use of electroless plating at temperatures below 100°C. Previous plating studies produced films with unacceptably high resistance. The Kansai University group tested several different plating chemistries, finding the best results with a succinic acid complexing agent followed by a post-deposition forming gas anneal. They believe that the anneal helps to desorb impurities originating from the plating bath. [5]
Christoph Adelmann and colleagues at imec observed that ruthenium is an anisotropic conductor, with about 25% lower resistivity along the hexagonal [001] axis. Unfortunately, this means that epitaxial thin films on silicon typically align the current flow with a high resistivity direction. Tests on sapphire substrates found that changing the film orientation can improve resistivity, but integrating epitaxial ruthenium metal into a CMOS process would only be possible with layer transfer techniques. [6]
While semiconductor manufacturers are constantly optimizing their processes, step changes like the introduction of a new dielectric or a new conductor happen slowly, only after fully exhausting the possibilities of the incumbent technology. Introducing ruthenium as either a via or line material would be such a change. It won’t happen soon, but the industry is clearly laying the foundation.
Related Reading
On-Die And In-Package Interconnects
A 94-page research report on interconnect fundamentals for semiconductor engineers.
Interconnects Approach Tipping Point
The 10 angstrom node will usher in new architectures, tooling, and materials, forcing a massive change in the way fabs build interconnects.
Ruthenium Interconnects On Tap
Chipmakers will stall as long as possible, but copper’s days are numbered.
New Interconnect Metals Need New Dielectrics
Options emerge for thin films that are viable at the most advanced nodes.
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