tag: imec

Chip Industry Technical Paper Roundup: April 2
By Linda Christensen - 02 Apr, 2024 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library. [table id=211 /] Find last week’s technical paper additions here. » read more

Chip Industry Week In Review
By The SE Staff - 29 Mar, 2024 - Comments: 0

By Adam Kovac, Karen Heyman, and Liz Allan.  China introduced strict procurement guidelines aimed at blocking the use of AMD and Intel processors in government computers. Meanwhile, China urged the Netherlands to ease restrictions on deep ultraviolet (DUV) litho equipment, according to Nikkei Asia. DUV is an older technology, based on 193nm ArF lasers, but in conjunction with multi-p... » read more

Optimizing Event-Based Neural Network Processing For A Neuromorphic Architecture
By Technical Paper Link - 28 Mar, 2024 - Comments: 0

A new technical paper titled "Optimizing event-based neural networks on digital neuromorphic architecture: a comprehensive design space exploration" was published by imec, TU Delft and University of Twente. Abstract "Neuromorphic processors promise low-latency and energy-efficient processing by adopting novel brain-inspired design methodologies. Yet, current neuromorphic solutions still str... » read more

Superconducting Qubits Made Using Industry-Standard, Advanced Semiconductor Manufacturing (imec, KU Leuven)
By Technical Paper Link - 25 Mar, 2024 - Comments: 0

A new technical paper titled "High-coherence superconducting qubits made using industry-standard, advanced semiconductor manufacturing" was published by researchers at imec and KU Leuven. Abstract: "The development of superconducting qubit technology has shown great potential for the construction of practical quantum computers. As the complexity of quantum processors continues to grow, the ... » read more

Powering CFETs From The Backside
By Katherine Derbyshire - 21 Mar, 2024 - Comments: 0

The first CMOS circuits to incorporate backside power connections are likely to be based on stacked nanosheet transistors, but further down the road, planners envision complementary transistors (CFETs) that vertically integrate stacked NFET and PFET devices. With at least twice the thickness of a nanosheet transistor, connecting CFETs to each other and to the rest of the circuit is likely to... » read more

Chip Industry Week In Review
By The SE Staff - 15 Mar, 2024 - Comments: 0

By Adam Kovac, Karen Heyman, and Liz Allan. Europe's semiconductor footprint is growing in areas that previously had little association with chips. Silicon Box plans to build a panel-level foundry in northern Italy, funded in part by the Italian government. The deal is worth around €3.2 billion ($3.6B). In addition, imec will establish a specialized 300mm chip technology pilot line in M... » read more

Backside Power Delivery Adds New Thermal Concerns
By Karen Heyman - 14 Mar, 2024 - Comments: 0

As the semiconductor industry gears up for backside power delivery at the 2nm node, implementation of the technology requires a re-thinking of established design practices. While some EDA tools are already qualified, designers must acquaint themselves with new issues, including making place-and-route more thermal-aware and how to manage heat dissipation with less shielding and thinner substr... » read more

Chip Industry Week In Review
By The SE Staff - 01 Mar, 2024 - Comments: 0

By Adam Kovac, Karen Heyman, and Liz Allan. India approved the construction of two fabs and a packaging house, for a total investment of about $15.2 billion, according to multiple sources. One fab will be jointly owned by Tata and Taiwan's Powerchip. The second fab will be a joint investment between CG Power, Japan's Renesas Electronics, and Thailand's Stars Microelectronics. Tata will run t... » read more

Backside Power Delivery Gears Up For 2nm Devices
By Laura Peters - 26 Feb, 2024 - Comments: 1

The top three foundries plan to implement backside power delivery as soon as the 2nm node, setting the stage for faster and more efficient switching in chips, reduced routing congestion, and lower noise across multiple metal layers. The benefits of using this approach are significant. By delivering power using slightly fatter, less resistive lines on the backside, rather than inefficient fro... » read more

Chip Industry Week In Review
By The SE Staff - 23 Feb, 2024 - Comments: 0

By Jesse Allen, Gregory Haley, and Liz Allan Intel officially launched Intel Foundry this week, claiming it's the "world's first systems foundry for the AI era." The foundry also showed off a more detailed technology roadmap down to expanded 14A process technology. Intel CEO Pat Gelsinger noted the foundry will be separate from the chipmaker, utilize third-party chiplets and IP, and leverage... » read more

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