tag: InFo

Extending The IC Roadmap
By Mark LaPedus - 11 Jun, 2018 - Comments: 0

An Steegen, executive vice president of semiconductor technology and systems at Imec, sat down with Semiconductor Engineering to discuss IC scaling and chip packaging. Imec is working on next-generation transistors, but it is also developing several new technologies for IC packaging, such as a proprietary silicon bridge, a cooling technology and packaging modules. What follows are excerpts of t... » read more

Toward High-End Fan-Outs
By Ed Sperling - 05 Mar, 2018 - Comments: 1

Foundries and OSATs are working on more advanced fan-outs, including some with vertically stacked die inside the package, filling a middle ground between lower-cost fan-outs and systems in package on one side and 2.5D and 3D-ICs on the other. These new [getkc id="202" kc_name="fan-outs"] have denser interconnects than previous iterations, and in some cases they include multiple routing layer... » read more

Fan-Out Wars Begin
By Mark LaPedus - 05 Feb, 2018 - Comments: 3

Several packaging houses are developing the next wave of high-density fan-out packages for premium smartphones, but perhaps a bigger battle is brewing in the lower density fan-out arena. Amkor, ASE, STATS ChipPAC and others sell traditional low-density fan-out packages, although some new and competitive technologies are beginning to appear in the market. Low-density fan-out, or sometimes cal... » read more

Advanced Packaging’s Progress
By Mark LaPedus - 09 Oct, 2017 - Comments: 0

Shim Il Kwon, CTO at STATS ChipPAC, sat down with Semiconductor Engineering to discuss the current and future trends of chip packaging. What follows are excerpts of that conversation. SE: The outsourced semiconductor assembly and test (OSAT) vendors provide third-party IC-packaging and test services. What are the big challenges for OSATs today? Shim: The OSAT market is very competitive, w... » read more

Challenges For Future Fan-Outs
By Mark LaPedus - 07 Jul, 2017 - Comments: 1

The fan-out wafer-level packaging market is heating up. At the high end, for example, several packaging houses are developing new fan-out packages that could reach a new milestone and hit or break the magic 1µm line/space barrier. But the technology presents some challenges, as it may require more expensive process flows and equipment like lithography. Fig. 1: Redistribution layers. Source: L... » read more

Wirebond Technology Rolls On
By Mark LaPedus - 08 May, 2017 - Comments: 2

Several years ago, many predicted the demise of an older interconnect packaging technology called wire bonding, prompting the need for more advanced packaging types. Those predictions were wrong. The semiconductor industry today uses several advanced packaging types, but wire bonding has been reinvented over the years and remains the workhorse in packaging. For example, Advanced Semiconducto... » read more

What Next For OSATs
By Mark LaPedus - 06 Mar, 2017 - Comments: 0

Semiconductor Engineering sat down to discuss IC-packaging and business trends with Tien Wu, chief operating officer at Taiwan’s Advanced Semiconductor Engineering ([getentity id="22930" comment="ASE"]), the world’s largest outsourced semiconductor assembly and test (OSAT) vendor. What follows are excerpts of that conversation. SE: What’s the outlook for the IC industry in 2017? Wu:... » read more

OSAT Biz: Growth And Challenges
By Mark LaPedus - 08 Feb, 2017 - Comments: 0

Amid a challenging business environment, the outsourced semiconductor assembly and test (OSAT) industry is projected to see steady to strong growth in a number of packaging segments this year. Right now, the [getkc id="83" kc_name="OSATs"]—which provide third-party IC-packaging and test services—are seeing brisk demand for both legacy and advanced chip packages. In addition, IDMs continu... » read more

Betting On Wafer-Level Fan-Outs
By Ed Sperling - 06 Feb, 2017 - Comments: 2

Advanced packaging is starting to gain traction as a commercially viable business model rather than just one more possible option, propelled by the technical difficulties in routing signals at 10nm and 7nm and skyrocketing costs of device scaling on a single die. The inclusion of a [getkc id="202" kc_name="fan-out"] package for logic in Apple's iPhone 7, based on TSMC's Integrated Fan-Out (... » read more

2017: Manufacturing And Markets
By Brian Bailey - 12 Jan, 2017 - Comments: 0

While the industry is busy chatting about the end of Moore's Law and a maturing of the semiconductor industry, the top minds of many companies are having none of it. A slowdown in one area is just an opportunity, in another and that is reflected in the predictions for this year. As in previous years, Semiconductor Engineering will look back on these predictions at the end of the year to see ... » read more

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