Advanced Packaging’s Progress

STATS ChipPAC’s CTO zeroes on different types of packages and what the pros and cons are for each.

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Shim Il Kwon, CTO at STATS ChipPAC, sat down with Semiconductor Engineering to discuss the current and future trends of chip packaging. What follows are excerpts of that conversation.

SE: The outsourced semiconductor assembly and test (OSAT) vendors provide third-party IC-packaging and test services. What are the big challenges for OSATs today?

Shim: The OSAT market is very competitive, with relentless pressure to reduce costs. Semiconductor companies are increasingly looking to their supply chain partners to develop complex, highly integrated solutions for their new end products across a wide range of applications. While advanced integration technologies, such as 2.5D, 3D or fan-out wafer-level packaging (FOWLP) and system-in-package (SiP), are expected to drive considerable growth in the industry, the significant investments required make the barrier to entry very high for most OSAT companies. Very few OSATs can afford to make the necessary investments in advanced packaging to achieve the production scale required. At the same time, however, we are making significant capital investments in R&D and manufacturing to expand advanced packaging capabilities.

SE: Another challenge is finding the next growth driver in the IC industry. The smartphone has been the big driver for chips, but the cell-phone market is slowing. What are the IC growth drivers that could take up the slack?

Shim: From an OSAT perspective, we see four main growth drivers of IC demand: (1) mmWave devices for 5G mobile, infrastructure, consumer and automotive products; (2) emerging artificial intelligence edge and cloud processors as well as accelerators; (3) IoT and wearable devices, including augmented reality/virtual reality (AR/VR), and (4) automotive ADAS-centric devices for electric vehicles and self-driving cars, including radar, LiDAR, sensor hubs and processors.

SE: Today, fan-out packaging is generating the most buzz in the market. In fan-out, the interconnects are fanned-out in the package, enabling more I/Os than traditional package types. Fan-out packages are being used for application processors in smartphones as well as for consumer chips. What are the future apps that will use fan-out packages?

Shim: The integration capabilities and design flexibility of FOWLP are driving adoption in a number of emerging market segments, such as IoT as well as wearable electronics such as health bands and cardiac monitoring devices. Other segments include fingerprint sensors, MEMS, 5G mmWave devices, and automotive applications, such as advanced driver assistance systems (ADAS). If the end application requires a reduction in form factor and a thinner package with a high level of integration, FOWLP can provide a superior solution.

SE: The fan-out market is fragmented. There are several flavors of fan-out, such as chip-first/face-down, chip-first/face-up, and chip-last. Can you describe each technology type?

Shim: In a chip-first approach, the chip is diced, attached to a temporary carrier and molded. Redistribution, ball drop and back-end processes are then completed to finish the package. In this approach, the die can be face down or face up during molding. The chip-first, face-down option is the lowest cost approach as it doesn’t require any bumping prior to molding. In a chip-first, face-up approach, copper column bumping occurs prior to dicing/attaching to a temporary carrier. After molding, grinding of the molding compound is done to reveal the copper column bumps before carrying out the redistribution process.

SE: What about chip-last?

Shim: In a chip-last approach, the redistribution layer is made on a sacrificial carrier first. The chip is attached to the RDL layer using flip-chip attach processes and then it is molded. The sacrificial carrier is removed after molding to expose the RDL surface to which ball drop and back-end processes are done to finish into a package. This approach requires the chips to be bumped with copper and/or solder so that they can be attached to the RDL. The use of a sacrificial carrier followed by the removal later in the process requires additional cost.


Fig. 1: Chip first vs. chip last. Source: TechSearch International

SE: Which flavor has the most traction?

Shim: Chip-first is the only approach that has been in volume production for close to a decade now, with yields that are comparable to other packaging technologies. The chip-last approach has not been widely adopted so far in the industry.

SE: Is there room for each fan-out technology in the market? How will this all play out?

Shim: Chip-first FOWLP is the most widely adopted solution in the industry today with multiple customers. Manufacturing services offered by multiple tier-one OSATs enable customers to have multi-sourcing options with a well-established supply chain. Meanwhile, the chip-last approach may be adopted for a niche application, such as relatively large-sized SoC or SiP products for better yield management.

SE: STATS ChipPAC was one of the early vendors in the fan-out market with a technology called embedded wafer level ball grid array (eWLB). What is eWLB?

Shim: Our experience in fan-out technology extends back to 2008, when we formed a manufacturing partnership with Infineon Technologies for eWLB technology. eWLB is a trade name for a chip-first, face-down FOWLP. Over the last nine years, we have invested significant resources and capital to develop a eWLB portfolio that includes small die, large die, side-by-side multi-die, MEMS, 2.5D and 3D package-on-package (PoP) and system-in-package (SiP) architectures. We have driven a number of eWLB technology achievements in the industry, such as dense vertical interconnections as high as 500 to 1,000 I/Os, very fine line and widths spacing down to 2µm/2µm and multi-layer RDL above 3 layers. eWLB has been successful in mobile applications with the largest demand in baseband processors, RF transceivers and power management ICs.

SE: Where is eWLB going in the future?

Shim: eWLB technology development will continue to move forward along three different pathways. The first is integrated solutions (multi-chip, multi-RDL), such as flip-chip eWLB and eWLB SiP with active and passive components. The second is high I/O density 2.5D/3D eWLB as a cost-effective alternative to TSV for high-performance devices. The third is mmWave package designs, which achieve higher frequencies, bandwidth and transmission performance in applications such as 77-GHz ADAS and 5G/WiGig antenna-in-package solutions.


Fig. 2: eWLB packaging. Source: STATS ChipPAC

SE: Today, many vendors are ramping up next-generation, high-density fan-out packages in the market. TSMC’s InFO fan-out technology is one example. But others are still trying to get a foothold in the market. What are some of the challenges here?

Shim: We have been in high volume production for over eight years now and have shipped over 1.5 billion units. With the significant growth of FOWLP in the industry over the last few years and rapidly expanding adoption by customers across multiple markets, it can be considered a mainstream packaging choice for customers. Unlike other mature technologies, FOWLP technology development is still ongoing and rapidly evolving in areas, such as 3D integration, SiP, MEMS and sensors. As FOWLP production volume continues to increase, there will be further optimizations in the manufacturing process, improved utilization and reduced material costs.

SE: What are some of the other challenges for fan-out?

Shim: Companies that are in the development phase or early production of FOWLP manufacturing do need to focus on their process and techniques to minimize die shift and warpage.

SE: What else?

Shim: Maintaining a high yield in high-volume manufacturing is essential for any new technology to be widely adopted. Another challenge that manufacturers face is maximizing panel utilization to achieve the lowest possible cost for a fan-out package. This is what drives the industry discussion on panel-level manufacturing. In 2016, we increased our wafer carrier sizes from 300mm to a high-density carrier size that is unique to our manufacturing process. We have been working on an even larger, rectangular panel-level process that we will implement when the economics make sense.

SE: In R&D, the industry has been developing a next-generation fan-out technology using a panel-level format. In panel-level fan-out packaging, you can put more die on a panel as compared to a traditional round wafer, which could potentially lower the cost for the technology. What are the advantages and challenges here?

Shim: Panel-level manufacturing provides the ability to significantly increase production output of FOWLP. Thanks to the success of the FOWLP platform, equipment makers show keen interest in developing the tools for panel-level processes and multiple consortiums have been kicked off in the last two years to take this towards high-volume manufacturing. For manufacturing companies, the investment cost required for a panel line is significant and a very large volume of packages are required to run the line efficiently for a positive return-on-investment. As a result, panel-level fan-out will materialize once the demand grows further.


Fig. 3: Comparison of number of die exposed on 300mm wafer to number of die on panel. Source: STATS ChipPAC, Rudolph

SE: For years, the industry has been shipping 2.5D/3D technology, a die stacking technique that promises to boost the bandwidth in devices. In 2.5D/3D, the package is on the bottom while the dies are on top. A silicon interposer is the bridge between them. Interposers have through-silicon vias (TSVs), which act as fast electrical signal conduits between the package and dies. What’s happening here?


Fig. 4: 2.5D with TSVs and high-bandwidth memory. Source: Samsung

Shim: Demand for 2.5D/3D TSV is growing with some devices in production, although it is currently a small niche due to limited applications and a closed supply chain. The markets where there is some traction for TSV technology include CMOS image sensors, memory, graphics and networking. 3D TSV is more suitable for applications where cost considerations are secondary to performance requirements. For high-density applications where cost is a concern, FOWLP is a more cost-effective and infrastructure-friendly alternative to TSVs.

SE: What are the challenges with 2.5D?

Shim: Cost will continue to be a big challenge with TSV technology along with the sourcing of silicon interposers for 2.5D solutions. In addition to the challenges with cost, infrastructure and the supply chain, 3D TSV technologies will still need to overcome a concern on KGD and testing for heterogeneous device integration.

SE: Traditional chip scaling is slowing down. Still, some say chip scaling will continue. Others say it will stop one day and that all chips will eventually end up in an advanced package. In either case, the buzzword is heterogeneous integration, where you integrate different dies in a package. How do you see the shift towards heterogeneous integration playing out at advanced nodes, say at 7nm and beyond?

Shim: It may depend on the speed of chip scaling and cost parity since heterogeneous integration in a package or SiP is an alternate or a bridging solution for a SoC. Beyond the 5nm silicon node, the need for heterogeneous integration will be more evident as it may make more economical sense. Regardless, the key considerations for heterogeneous integration in packaging are: 1) density of the interposer to bridge the gap between the nanometer scale of a chip and the micrometer scale of the packaging substrate; and 2) manufacturing scalability with a high yield using the interposer or equivalent.

SE: There are several types of schemes for heterogeneous integration, including fan-out, 2.5D/3D, and even chiplets. How will this all play out?

Shim: From a packaging technology perspective, wafer- or panel-level 3D fan-out and/or 2.5D technologies seem more practical to meet the requirements. 3D technology with wafer-to-wafer bonding will be adopted more for homogeneous integration. TSV-based 3D heterogeneous integration may take more time to emerge due to lack of an EDA solution and readiness in the supply chain.

SE: So there are several ways to implement heterogeneous integration. Will all of these approaches prevail in the long term?

Shim: There may be no prevailing technology, and instead, they will co-exist as time goes by since the platform for heterogeneous integration will be diversified based on the application or the complexity of integration and performance. However, 2.5D or fan-out-based 3D technologies will be more visible in various applications.

SE: Is there something missing to make heterogeneous integration a more mainstream technology at advanced nodes?

Shim: The development of a process design kit (PDK) and electronic design automation (EDA) as well as the solution for system-level testing will be challenges for complicated integration solutions. In addition, a lower cost solution for high-density (≤=2µm line and space) interposer and finer pitch (≤=40µm) interconnect will be a key enabler for heterogeneous integration to become a mainstream technology going forward.

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