Heterogeneous Cache Coherence Requires A Common Internal Protocol


Machine learning and artificial intelligence systems are driving the need for systems-on-chip containing tens or even hundreds of heterogeneous processing cores. As these systems expand in size and complexity, it becomes too difficult to manage data flow solely through software means. An approach that simplifies software while improving performance and power consumption is to implement hardware... » read more

Shhhhh… Deadlocks Anonymous In Session


I am sure there is an anonymous group – like Alcoholics Anonymous – headquartered in Silicon Valley, meeting every quarter to discuss the deadlocks that have paralyzed their products, roadmap and deployments. In discreet venues in every town, small groups of engineers huddle together to share war stories about the disgruntled customers whose trust was lost because of a deadlock discovered o... » read more

New BEOL/MOL Breakthroughs?


Chipmakers are moving ahead with transistor scaling at advanced nodes, but it's becoming more difficult. The industry is struggling to maintain the same timeline for contacts and interconnects, which represent a larger portion of the cost and unwanted resistance in chips at the most advanced nodes. A leading-edge chip consists of three parts—the transistor, contacts and interconnects. The ... » read more

Changing Direction In Chip Design


Andrzej Strojwas, chief technologist at PDF Solutions and professor of electrical and computer engineering at Carnegie Mellon University—and the winner of this year's Phil Kaufman Award for distinguished contributions to EDA—sat down with Semiconductor Engineering to talk about device scaling, why the semiconductor industry will begin to fragment around new architectures and packaging, and ... » read more

Fab Tool Biz Faces Challenges In 2017


After experiencing a gradual recovery and positive growth in 2016, the semiconductor equipment industry sees a mixed picture as well as some uncertainty in 2017. In the near term, though, business is robust. Several chipmakers started to place a sizeable number of fab tool orders in the latter part of 2016, particularly in three areas—3D NAND, logic and foundry. Now, after buying the in... » read more

Power/Performance Bits: Nov. 15


Another record-breaking tandem perovskite solar cell University of California, Berkeley, and Lawrence Berkeley National Laboratory scientists report a new design for perovskite solar cells that achieves an average steady-state efficiency of 18.4%, with a high of 21.7% and a peak efficiency of 26%. "This has a great potential to be the cheapest photovoltaic on the market, plugging into any... » read more

Stacked Die Changes


Semiconductor Engineering sat down to discuss advanced packaging with David Pan, associate professor in the department of electrical and computer engineering at the University of Texas; Max Min, senior technical manager at [getentity id="22865" e_name="Samsung"]; John Hunt, senior director of engineering at ASE; and Sitaram Arkalgud, vice president of 3D portfolio and technologies at Invensas. ... » read more

Adapt Or Perish: A Unified Theory Of Coherency


Evolution is a natural process and more importantly a relatively slow process that has eventually got us here, capable of perceiving, analyzing, and handling complex tasks. As our environment, society, and surroundings became more complex we learned how to adapt at a brisk and instantaneous manner, in this melting pot of a heterogeneous world. The evidence can be seen in all ages, from the poli... » read more

From Game Theory To The Unified Theory of Coherency


Adam Smith said that the best result comes from everyone in the group doing what is best for himself. But he’s only half right because the best result would come from everyone in the group doing what is best for himself and the group. If you are wondering where you might have heard this before, it was Russell Crowe playing John Nash in the movie “A Beautiful Mind.” John Nash was an Ame... » read more

Next Challenge: Contact Resistance


In chip scaling, there is no shortage of challenges. Scaling the finFET transistor and the interconnects are the biggest challenges for current and future devices. But now, there is another part of the device that’s becoming an issue—the contact. Typically, the contact doesn’t get that much attention, but the industry is beginning to worry about the resistance in the contacts, or conta... » read more

← Older posts Newer posts →