Adapt Or Perish: A Unified Theory Of Coherency

By Rajesh Ramanujam - 28 Jul, 2016 - Comments: 0

Evolution is a natural process and more importantly a relatively slow process that has eventually got us here, capable of perceiving, analyzing, and handling complex tasks. As our environment, society, and surroundings became more complex we learned how to adapt at a brisk and instantaneous manner, in this melting pot of a heterogeneous world. The evidence can be seen in all ages, from the poli... » read more

From Game Theory To The Unified Theory of Coherency

By Rajesh Ramanujam - 30 Jun, 2016 - Comments: 0

Adam Smith said that the best result comes from everyone in the group doing what is best for himself. But he’s only half right because the best result would come from everyone in the group doing what is best for himself and the group. If you are wondering where you might have heard this before, it was Russell Crowe playing John Nash in the movie “A Beautiful Mind.” John Nash was an Ame... » read more

Next Challenge: Contact Resistance

By Mark LaPedus - 23 Jun, 2016 - Comments: 0

In chip scaling, there is no shortage of challenges. Scaling the finFET transistor and the interconnects are the biggest challenges for current and future devices. But now, there is another part of the device that’s becoming an issue—the contact. Typically, the contact doesn’t get that much attention, but the industry is beginning to worry about the resistance in the contacts, or conta... » read more

Executive Insight: K. Charles Janac

By Ed Sperling - 24 May, 2016 - Comments: 0

K. Charles Janac, chairman and CEO of Arteris, sat down with Semiconductor Engineering to talk about what's changing in the automotive market, the impact of big data, and heterogeneous cache coherency. What follows are excerpts of that discussion. SE: What are the big changes you're seeing in semiconductor design? Janac: There are a lot of changes right now. Mobility is slowing down and b... » read more

High-Bandwidth Memory

By eSilicon - 27 Apr, 2016 - Comments: 0

High-bandwidth memory (HBM) is a JEDEC-defined standard, dynamic random access memory (DRAM) technology that uses through-silicon vias (TSVs) to interconnect stacked DRAM die. In its first implementation, it is being integrated with a system-on-chip (SoC) logic die using 2.5D silicon interposer technology. This white paper explains HBM’s value proposition, and how these five companies make... » read more

7nm Fab Challenges

By Mark LaPedus - 21 Apr, 2016 - Comments: 3

Leading-edge foundry vendors have made the challenging transition from traditional planar processes into the finFET transistor era. The first [getkc id="185" kc_name="finFETs"] were based on the 22nm node, and now the industry is ramping up 16nm/14nm technologies. Going forward, the question is how far the finFET can be scaled. In fact, 10nm finFETs from Samsung are expected to ramp by ye... » read more

The First Fully Configurable Cache-Coherent Interconnect Solution For SoCs

By NetSpeed Systems - 23 Mar, 2016 - Comments: 0

The last few decades have seen a massive growth in the number of CPU cores, computing clusters and other IP blocks in a SoC. This massive growth along with the need for complex chip integration has driven the need for sophisticated interconnects. SoC architects have employed a variety of methods from buses to crossbars to handcrafted NoCs with Lego-like blocks with varying degrees of success. T... » read more

An Architecture Synthesis Platform For Rapidly Evolving SoC Designs

By NetSpeed Systems - 24 Feb, 2016 - Comments: 0

Modern System-on-Chip (SoC) architects are faced with a number of serious challenges. First, the number of Semiconductor Intellectual Property (IP) blocks in SoC designs is growing continuously and increasing design complexity. With IP design reuse becoming more common, the mixing and matching of IP components is further compounding design complexity. Second, sophisticated SoC applications are ... » read more

5nm Fab Challenges

By Mark LaPedus - 21 Jan, 2016 - Comments: 2

At a recent event, Intel presented a paper that generated sparks and fueled speculation regarding the future direction of the leading-edge IC industry. The company described a next-generation transistor called the nanowire FET, which is a finFET turned on its side with a gate wrapped around it. Intel’s nanowire FET, sometimes called a gate-all-around FET, is said to meet the device require... » read more

Interconnect Challenges Grow

By Mark LaPedus - 20 Aug, 2015 - Comments: 1

It’s becoming apparent that traditional chip scaling is slowing down. The 16nm/14nm logic node took longer than expected to unfold. And the 10nm node and beyond could suffer the same fate. So what’s the main cause? It’s hard to pinpoint the problem, although many blame the issues on lithography. But what could eventually hold up the scaling train, and undo Moore’s Law, is arguably t... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: interconnects