tag: interconnects

PIO on Current HW Outperforms DMA Over a Range of Payload Sizes In A Number of Different Applications (ETH Zurich)
By Technical Paper Link - 11 Oct, 2024 - Comments: 0

A new technical paper titled "Rethinking Programmed I/O for Fast Devices, Cheap Cores, and Coherent Interconnects" was published by researchers at ETH Zurich. Abstract: "Conventional wisdom holds that an efficient interface between an OS running on a CPU and a high-bandwidth I/O device should be based on Direct Memory Access (DMA), descriptor rings, and interrupts: DMA offloads transfers fr... » read more

Enabling Innovative Multi-Vendor Chiplet-Based Designs
By Elad Alon - 26 Sep, 2024 - Comments: 0

Chiplets have emerged as a critical implementation paradigm for semiconductor products, primarily because they can deliver cost benefits relative to a non-chiplet-based approach. The first, most well-proven, and obvious benefit of a chiplet-based approach is manufacturing cost. Manufacturing cost benefits are accrued either from the appropriate selection of chiplet die size, or by optimizin... » read more

Managing Performance in Modern SoC Designs
By John Min - 26 Sep, 2024 - Comments: 0

As industries like automotive, consumer electronics, telecommunications and artificial intelligence (AI) push for greater processing power, efficiency and scalability, system-on-chip (SoC) designs have rapidly evolved to meet these demands. With the growing complexity of modern SoCs, designers face the challenge of managing an increasing number of interconnected IP blocks while ensuring seamles... » read more

Simultaneous Bi-Directional Signaling: A Breakthrough Alternative For Multi-Die Assemblies
By Ramin Farjadrad - 29 Aug, 2024 - Comments: 0

In designing multi-die systems-in-package, with or without chiplets, it is easy to think of the interconnect between dies as simply analogous to the interconnect between functional blocks on a single die. But this analogy can lead architects and designers into a blind alley from which it becomes impossible to meet system performance and power requirements. The reason lies in fundamental differe... » read more

Characterizing Three Supercomputers: Multi-GPU Interconnect Performance
By Technical Paper Link - 27 Aug, 2024 - Comments: 0

A new technical paper titled "Exploring GPU-to-GPU Communication: Insights into Supercomputer Interconnects" was published by researchers at Sapienza University of Rome, University of Trento, Vrije Universiteit Amsterdam, ETH Zurich, CINECA, University of Antwerp, IBM Research Europe, HPE Cray, and NVIDIA. Abstract "Multi-GPU nodes are increasingly common in the rapidly evolving landscape... » read more

Here At Last! Automated Verification Of Heterogeneous 2D/3D Package Connectivity
By Michael Walsh - 25 Jul, 2024 - Comments: 0

By Michael Walsh and Jin Hou with Todd Burkholder The heterogeneous integration of multiple ICs in a single package along with high-performance, high-bandwidth memory is critical for many high-performance computing applications. After everything has been heterogeneously integrated and packaged, such designs feature complex connectivity with many hundreds of thousands of connections, making i... » read more

Optimizing Interconnect Topologies For Automotive ADAS Applications
By Ashley Stevens - 25 Jul, 2024 - Comments: 0

Designing automotive Advanced Driver Assistance Systems (ADAS) applications can be incredibly complex. State-of-the-art ADAS and autonomous driving systems use ‘sensor fusion’ to combine inputs from multiple sources, typically cameras and optionally radar and lidar units to go beyond passive and active safety to automate driving. Vision processing systems combine specialized AI accelerators... » read more

Essential Insights for Design PCIe 6.0 Interconnects
By Keysight - 24 Jul, 2024 - Comments: 0

PCI Express (PCIe) is a serial communication protocol that has progressed through generations to enhance data rates and functionality. The latest version, PCIe 6.0, doubles the data rate to 64 GT/s, enabling up to 256 GB/s of bandwidth in an x16 configuration. The technology incorporates PAM4 signaling and forward error correction to maintain high speeds with improved signal integrity and relia... » read more

Survey of CXL Implementations and Standards (Intel, Microsoft)
By Technical Paper Link - 22 Jul, 2024 - Comments: 0

A new technical paper titled "An Introduction to the Compute Express Link (CXL) Interconnect" was published by researchers at Intel Corporation, Microsoft, and University of Washington. Abstract "The Compute Express Link (CXL) is an open industry-standard interconnect between processors and devices such as accelerators, memory buffers, smart network interfaces, persistent memory, and solid-... » read more

SiC Power Electronics Packaging: Floating Die Structure and Liquid Metal Fluidic Connection (Cambridge U. )
By Technical Paper Link - 17 Jul, 2024 - Comments: 0

A new technical paper titled "Liquid Metal Fluidic Connection and Floating Die Structure for Ultralow Thermomechanical Stress of SiC Power Electronics Packaging" was published by researchers at Cambridge University. Abstract "Coefficients of thermal expansion (CTE) of various materials in packaging structure layers vary largely, causing significant thermomechanical stress in power electroni... » read more

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