tag: interfaces

Designs Beyond The Reticle Limit
By Brian Bailey - 12 Nov, 2020 - Comments: 0

Designs continue to grow in size and complexity, but today they are reaching both physical and economic challenges. These challenges are causing a reversal of the integration trend that has provided much of the performance and power gains over the past couple of decades. The industry, far from giving up, is exploring new ways to enable designs to go beyond the reticle size, which is around 8... » read more

PCIe 5.0: A Key Interface Solution For The Evolving Data Center
By Vinitha Seevaratnam - 10 Sep, 2020 - Comments: 0

A great many developments are shaping the evolution of the data center. Enterprise workloads are increasingly shifting to the cloud, whether these be hosted or colocation implementations. The nature of workload traffic is changing such that data centers are architected to manage greater east-west (within the data center) communication. New workloads, with AI/ML (artificial intelligence/machine ... » read more

Efficient Sensitivity-Aware Assessment Of High-Speed Links Using PCE And Implications For COM
By Mentor, a Siemens Business - 09 Sep, 2020 - Comments: 0

This technical white paper, originally presented at DesignCon, investigates the challenges of increased data rates and reduced margins in high-speed link design. Section 1: Introduction Section 2: State of the Art Link Evaluation and Assessment of Parameter Variability Section 3: Proposed Modeling Framework Section 4: Sensitivity Analysis of a High-Speed Interconnect Section 5: Conclusio... » read more

PCIe Simulation Speed-Up Using Mentor QVIP With PLDA PCIe Controller For DMA Applications
By Mentor, a Siemens Business - 12 Aug, 2020 - Comments: 0

In this case study, PLDA explains how verification engineers can use Mentor’s Questa Verification IP (QVIP) to improve productivity during the functional verification of PCIe designs with DMA engines. The flexibility of Questa VIP was key to creating custom testbenches from scratch that can dynamically adapt to different IP topologies and configurations, mixing PCIe interfaces with multiple A... » read more

Conflicting Demands At The Edge
By Ed Sperling - 04 Jun, 2020 - Comments: 0

Semiconductor Engineering sat down to define what the edge will look like with Jeff DeAngelis, managing director of the Industrial and Healthcare Business Unit at Maxim Integrated; Norman Chang, chief technologist at Ansys; Andrew Grant, senior director of artificial intelligence at Imagination Technologies; Thomas Ensergueix, senior director of the automotive and IoT line of business at Arm; V... » read more

What’s So Important About Processor Extensibility?
By Brian Bailey - 28 May, 2020 - Comments: 1

While the ability to extend a processor is nothing new, market dynamics are forcing a growing percentage of the industry to consider it a necessary part of their product innovation. From small IoT functions to massive data centers and artificial intelligence, the need to create an optimized processing platform is often the only way to get more performance or lower power out of the silicon area ... » read more

Who Owns A Car’s Chip Architecture
By Ed Sperling - 05 May, 2020 - Comments: 0

Kurt Shuler, vice president of marketing at Arteris IP, examines the competitive battle brewing between OEMs and Tier 1s over who owns the architecture of the electronic systems and the underlying chip hardware. This has become a growing point of contention as both struggle for differentiation in a market where increasingly autonomous vehicles will all behave the same way. That, in turn, has si... » read more

Waiting For Chiplet Interfaces
By Brian Bailey - 13 Jun, 2019 - Comments: 0

There aren't many success stories related to chiplets today for a very simple reason—there are few standard interfaces defined for how to connect them. In fact, the only way to use them is to control both sides of the interface with a proprietary interface and protocol. The one exception is the definition of HBM2, which enables large quantities of third-party DRAM to be connected to a logi... » read more

Next-Generation Ethernet Interconnects For 400G Hyperscale Data Centers
By Rita Horner - 08 Nov, 2018 - Comments: 0

The need for higher bandwidth with efficient connectivity increases as hyperscale data centers transition to faster, flatter, and more scalable network architectures, such as the 2-tier leaf-spine, as seen in Figure 1. The leaf-spine architecture requires massive interconnects as each leaf switch fans-out to every spine switch, maximizing connectivity between servers. Hardware accelerators, art... » read more

Tech Talk: Analog Simplified
By Ed Sperling - 16 Apr, 2018 - Comments: 0

Benjamin Prautsch, Fraunhofer EAS' group manager for advanced mixed-signal automation, talks about how to simplify and speed up analog IP development, its role in IoT and IIoT/Industry 4.0, and why this is becoming so important for advanced packaging and advanced process nodes. https://youtu.be/6ISL1A7Wy_I » read more

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