tag: IP reuse

Utilizing IP Lifecycle to Author IP for Successful Reuse
By Cliosoft - 01 Apr, 2020 - Comments: 0

Successful reuse of IP relies on the entire IP lifecycle. Developing and maintaining documentation, reference designs and test suites requires a significant effort. Learn how they are vital for reuse in this white paper. Click here to read more. » read more

Tracking Re-Use Of Design IPs
By Amit Varde - 24 Feb, 2020 - Comments: 0

Design teams have a great incentive to create design blocks or IPs that can be reused: Each time an IP is successfully reused, precious time is saved from project schedule. Of course, as easy as it sounds, achieving this goal in real life is not simple. In reality, the observation is that design libraries cannot be used as-is by multiple projects. Consider this scenario: A smart new graduate... » read more

What’s In Your IP?
By Ed Sperling - 21 Feb, 2020 - Comments: 0

Jeff Markham, software architect at ClioSoft, talks with Semiconductor Engineering about IP traceability in markets such as automotive and aerospace, what’s actually in IP, what should not be in that IP from a security standpoint, and how all of this data can used to avert system reliability issues in the future. » read more

Challenges In IP Reuse
By Ed Sperling - 09 Dec, 2019 - Comments: 0

Jeff Markham, software architect at ClioSoft, explains why IP reuse is so important in advanced process node SoC chip designs, what companies need to keep track of when working with third-party IP, and how it needs to be characterized. » read more

IP Management And Development At 5/3nm
By Ann Mutschler - 24 Oct, 2019 - Comments: 1

The growing complexity of moving to new process nodes is making it much more difficult to create, manage and re-use IP. There are more rules, more data to manage, and more potential interactions as density increases, both in planar implementations and in advanced packaging. And the problems only get worse as designs move to 5nm and 3nm, and as more heterogeneous components such as accelerato... » read more

SOC Design & IP Management—A Must For Functional Verification
By Cliosoft - 05 Jun, 2019 - Comments: 0

As a part of the verification flow, verification teams perform different types of simulations based on the nature of the design. The simulations include digital logic functional simulations, mixed-signal functional simulations, power-aware simulations, formal verification runs and gate-level simulations. For a signoff, all planned tests must pass in all four types of simulations. In addition t... » read more

The Rapid Success Of IP Reuse
By Ranjit Adhikary - 13 May, 2019 - Comments: 0

The rise of IP use and reuse quickly became a challenge in the early 1990s as designs became more complex. Design teams quickly found themselves struggling to manage not only the vast numbers of IP cores that they were reusing but also versioning, permissions, legal approvals and so on. In the 1990s, software developers were established users of software configuration management (SCM) tools ... » read more

Design Reuse Vs. Abstraction
By Ann Mutschler - 05 Jul, 2018 - Comments: 1

Chip designers have been constantly searching for a hardware description language abstraction level higher than RTL for a few decades. But not everyone is moving in that direction, and there appear to be enough options available through design reuse to forestall that shift for many chipmakers. Pushing to new levels of abstraction is frequent topic of discussion in the design world, particula... » read more

Don’t Be The Dinosaur On IP Reuse
By Ranjit Adhikary - 07 Jun, 2018 - Comments: 0

In today’s competitive marketplace, IP assets are becoming more critical and strategic than ever before. There is a general understanding among all design companies that one needs to invest and reuse IPs within the enterprise for faster realization of an IP sub-system or an SoCs. Unfortunately, from the start most companies have failed to adopt the processes for developing and reusing their I... » read more

designHUB: Design Reuse Made Real
By Cliosoft - 06 Jun, 2018 - Comments: 0

It’s no secret: You can’t get to market quickly or efficiently without integrating and re-using IP technology in your system-on-chip (SoC) design. In the past 10 years alone, design re-use has doubled to the point where today you’ll find more than 150 reused blocks comprising 60-70% of the die area in an average SoC. The companies most successful with their IP-reuse strategies are thos... » read more

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