tag: IP

EDA, IP Grow 16.3%
By Ed Sperling - 08 Jul, 2019 - Comments: 0

EDA and IP revenue rebounded in Q1, with all geographies reporting increases, according to the ESD Alliance Market Statistics Service. Total revenue increased to 16.3% to $2.606 billion, up from $2.241 billion in the same period in 2018. The global numbers do not reflect the impact of a trade war between the United States and China, which occurred in Q2, but they do point to a significant re... » read more

Security’s Very Strange Path To Success
By Ed Sperling - 02 Jul, 2019 - Comments: 0

Security at the chip level appears to be heading toward a more promising future. The reason is simple—more people are willing to pay for security than in the past. For the most part, security is like insurance. You don't know it's working until something goes wrong, and you don't necessarily even know right away if there has been a breach. Sometimes it takes years to show up, because it ca... » read more

Enabling The RISC-V Ecosystem
By Tom Anderson - 27 Jun, 2019 - Comments: 0

Earlier this year, OneSpin’s Sven Beyer discussed the emerging RISC-V processor and some of its verification challenges. He stated that “RISC-V is hot and stands at the beginning of what may be a major shift in the industry.” In the few intervening months, it has become even more apparent that RISC-V is fundamentally changing system-on-chip (SoC) development. Dozens of commercial and open... » read more

Complete Formal Verification of RISC V Processor IPs for Trojan-Free Trusted ICs
By OneSpin Solutions - 26 Jun, 2019 - Comments: 0

RISC-V processor IPs are increasingly being integrated into system-on-chip designs for a variety of applications. However, there is still a lack of dedicated functional verification solutions supporting high-integrity, trusted integrated circuits. This paper examines an efficient, novel, formal-based RISC-V processor verification methodology. The RISC-V ISA is formalized in a set of Operational... » read more

Building Your First Chip For Artificial Intelligence? Read This First
By Ron Lowman - 13 Jun, 2019 - Comments: 0

As artificial intelligence (AI) capabilities enter new markets, the IP selected for integration provides the critical components of the AI SoC. But beyond the IP, designers are finding a clear advantage in leveraging AI expertise, services, and tools to ensure the design is delivered on time, with a high level of quality and value to the end customer for new and innovative applications. Over... » read more

Waiting For Chiplet Interfaces
By Brian Bailey - 13 Jun, 2019 - Comments: 0

There aren't many success stories related to chiplets today for a very simple reason—there are few standard interfaces defined for how to connect them. In fact, the only way to use them is to control both sides of the interface with a proprietary interface and protocol. The one exception is the definition of HBM2, which enables large quantities of third-party DRAM to be connected to a logi... » read more

BiST Grows Up In Automotive
By Ann Mutschler - 12 Jun, 2019 - Comments: 0

Test concepts and methods that have been used for many years in traditional semiconductor and SoC design are now being leveraged for automotive chips, but they need to be adapted and upgraded to enable monitoring of advanced automotive systems during operation of a vehicle. Automotive and safety critical designs have very high quality, reliability, and safety requirements, which pairs pe... » read more

How To Meet Power Performance And Cost for Autonomous Vehicle Systems Using Speedcore eFPGAs
By Achronix - 05 Jun, 2019 - Comments: 0

In the advanced, fully autonomous, self-driving vehicles of the future, the existence of dozens and even hundreds of distributed CPUs and numerous other processing elements is assured. Peripheral sensor-fusion and other processing tasks can be served by ASICs, SoCs, or traditional FPGAs. But the introduction of embedded FPGA blocks such as Achronix's Speedcore eFPGA IP provides numerous system-... » read more

Using Synopsys Z01X To Accelerate The Fault Injection Campaign Of A Fully Configurable IP
By Arteris - 05 Jun, 2019 - Comments: 0

By Arteris IP Alexis Boutillier, Corporate Application Manager, Safety Manager, and Mohan Krishnareddy, Solution Engineer, at the Synopsys Users Group (SNUG), March 2018, Santa Clara, CA. Principles and real-world practices of ISO 26262 for semiconductor design teams. After providing an overview of how functional safety affects management, development, and supporting processes, the paper exp... » read more

CEO Outlook: It Gets Much Harder From Here
By Ed Sperling - 03 Jun, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss what's changing across the semiconductor industry with Wally Rhines, CEO emeritus at Mentor, a Siemens Business; Jack Harding, president and CEO of eSilicon; John Kibarian, president and CEO of PDF Solutions; and John Chong, vice president of product and business development for Kionix. What follows are excerpts of that discussion, which was held in... » read more

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