tag: IP

Fibonacci And Honey Bees Have Something In Common: A Sweet Spot For Formal
By Sergio Marchese - 28 Mar, 2019 - Comments: 0

Time flies and the OneSpin’s Holiday Puzzle tradition has reached its third year. In December 2016, OneSpin challenged engineers everywhere to solve the Einstein riddle using assertions and a formal verification tool. In December 2017, the challenge was to model the hardest Sudoku in the world using assertions and find a solution with a formal tool. In addition, participants had to prove that... » read more

Using Less Power At The Same Node
By Brian Bailey - 14 Mar, 2019 - Comments: 0

Going to the next node has been the most effective way to reduce power, but that is no longer true or desirable for a growing percentage of the semiconductor industry. So the big question now is how to reduce power while maintaining the same node size. After understanding how the power is used, both chip designers and fabs have techniques available to reduce power consumption. Fabs are makin... » read more

How To Build An Automotive Chip
By Ann Mutschler - 07 Mar, 2019 - Comments: 0

The introduction of advanced electronics into automotive design is causing massive disruption in a supply chain that, until very recently, hummed along like a finely tuned sports car. The rapid push toward autonomous driving has changed everything. This year, Level 3 autonomy will begin hitting the streets, and behind the scenes, work is underway to design SoCs for Level 4. But how these chi... » read more

Embedded FPGA Basics
By Flex Logix - 06 Mar, 2019 - Comments: 0

You do not need know about FPGAs to integrate reconfigurable RTL into your SoC: our software maps your RTL into our EFLX array for you.  But if you are curious, read on. FPGAs are field programmable gate arrays. They offer a different kind of programmability from processors.  Processors are sequential while FPGAs enable massive parallelism.  A processor has one adder, one multiplier—an ... » read more

Collaborative IC Design Mandates Integrated Data Management
By Cliosoft - 11 Feb, 2019 - Comments: 0

Over the last decade, design teams have encountered increased competition due to globalization (requiring the best available engineers irrespective of location), an exponential increase in design complexity, and shrinking market windows. This results in teams of engineers with different skill sets (for example analog, digital, MEMS, and RF), spread across multiple sites, managing complex flows,... » read more

ISO 26262:2018, 2nd Edition: What Changes?
By Kurt Shuler - 07 Feb, 2019 - Comments: 0

If you’re involved somehow in design for automotive electronics, you probably have more than a cursory understanding of the ISO 26262 standard. What your organization is working from is most likely the 2011 definition. The most recent update is formally known as ISO 26262:2018, less formally as ISO 26262 2nd Edition. Figure 1. Overview of the ISO 26262:2018 series of standards (Source IS... » read more

Pushing AI Into The Mainstream
By Brian Bailey - 31 Jan, 2019 - Comments: 0

Artificial intelligence is emerging as the driving force behind many advancements in technology, even though the industry has merely scratched the surface of what may be possible. But how deeply AI penetrates different market segments and technologies, and how quickly it pushes into the mainstream, depend on a variety of issues that still must be resolved. In addition to a plethora of techni... » read more

Realizing the Benefits of 14/16nm Technologies
By eSilicon - 31 Jan, 2019 - Comments: 0

The scaling benefits of Moore’s Law are challenging below 28nm. It is no longer a given that the cost per gate will go down at process nodes below 28nm, e.g., 20nm though 14nm and 7nm. Rising design and manufacturing costs are contributing factors to this trend. Meanwhile, the competing trend of fewer but more complex system-on-chip (SoC) designs is reducing the knowledge base of many chip... » read more

EDA Grabs Bigger Slice Of Chip Market
By Brian Bailey - 31 Jan, 2019 - Comments: 0

EDA revenues have been a fairly constant percentage of semiconductor revenues, but that may change in 2019. With new customers creating demand, and some traditional customers shifting focus from advanced nodes, the various branches of the EDA tool industry may be where sticky technical problems are solved. IC manufacturing, packaging and development tools all are finding new ways to handle t... » read more

Chips&Media: Design and Verification of Deep Learning Object Detection IP
By Mentor, a Siemens Business - 30 Jan, 2019 - Comments: 0

Chips&Media, a leading provider of high-performance video IP for SoC design, took a unique approach to designing their latest IP for detecting objects in real time. They decided to adopt a new High-Level Synthesis (HLS) flow to implement their deep learning algorithm. But, they would have an RTL team create this algorithm, using traditional tools and another team would employ the Catapult H... » read more

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