tag: IP

Domain Crossing Nightmares
By Brian Bailey - 27 Sep, 2018 - Comments: 1

Semiconductor Engineering sat down to discuss problems associated with domain crossings with Alex Gnusin, design verification technologist for Aldec; Pete Hardee, director, product management for Cadence; Joe Hupcey, product manager and verification product technologist for Mentor, a Siemens Business; Sven Beyer, product manager design verification for OneSpin; and Godwin Maben, applications en... » read more

IP For Centralized ADAS Domain Controllers
By Synopsys - 12 Sep, 2018 - Comments: 0

A centralized architecture is becoming more popular to integrate the ADAS applications into a centralized ADAS domain controller. A centralized architecture reduces cost, minimizes development of separate software applications and reduces system complexity. As automakers adopt multi-domain controllers with centralized ADAS processors, the required performance and functionality of the ADAS proce... » read more

Week in Review: IoT, Security, Auto
By Jeff Dorsch - 07 Sep, 2018 - Comments: 0

Internet of Things Silicon Labs worked with Norway’s Q-Free to create the ParQSense Smart Parking Sensor, which helps drivers find available outdoor parking spaces. ParQSense uses the chip company’s Wonder Gecko wireless microcontroller for connectivity and control. Having gone through pilot testing in the European Union and North America this year, ParQSense is being released for commerci... » read more

Week In Review: Design, Low Power
By Jesse Allen - 17 Aug, 2018 - Comments: 0

Intel disclosed a speculative execution side-channel attack method called L1 Terminal Fault (L1TF). Leslie Culbertson, Intel's executive vice president and general manager of Product Assurance and Security, writes: "This method affects select microprocessor products supporting Intel Software Guard Extensions (Intel SGX) and was first reported to us by researchers at KU Leuven University, Techni... » read more

Impact Of IP On AI SoCs
By Ron Lowman - 09 Aug, 2018 - Comments: 2

The combination of mathematics and processing capability has set in motion a new generation of technology advancements with an entire new world of possibilities related to Artificial Intelligence. AI mimics human behavior using deep learning algorithms. Neural networks are what we define as deep learning, which is a subset of machine learning, which is yet a subset of AI, as shown in Figure 1. ... » read more

Embedded FPGA Timing
By Ed Sperling - 03 Aug, 2018 - Comments: 0

Namit Varma, senior director of Achronix’s India Technology Center, explains how to time an eFPGA, what can go wrong, what are the different clocking scenarios, and what impact variation has on the process. https://youtu.be/Jq4XUKnniB4 » read more

Not Enough Respect For SoC Interconnect
By K. Charles Janac - 30 Jul, 2018 - Comments: 0

For high-volume system-on-chip (SoC) applications—artificial intelligence (AI), automotive, mobility, solid state drives and more—effective interconnect technology can generate hundreds of millions of dollars in revenue due to smaller chip area, better functionality and faster delivery of SoC platforms. State-of-the-art interconnect technology also allows chip designers to create SoC deriva... » read more

Solving Systemic Complexity
By Ed Sperling - 26 Jul, 2018 - Comments: 0

EDA and IP companies have begun branching out in entirely new directions over the past 12 to 18 months, pouring resources into entirely different problems than electrostatic issues and routing complexity. While they're still focused on solving complexity at 10/7/5nm, they also recognize that enabling Moore's Law isn't the only opportunity. For an increasing number of new and established chip... » read more

Debug Issues Grow At New Nodes
By Ann Mutschler - 26 Jul, 2018 - Comments: 0

Debugging and testing chips is becoming more time-consuming, more complicated, and significantly more difficult at advanced nodes as well as in advanced packages. The main problem is that there are so many puzzle pieces, and so many different use cases and demands on those pieces, that it's difficult to keep track of all the changes and potential interactions. Some blocks are "on" sometimes,... » read more

On-Chip Monitoring Of FinFETs
By Ed Sperling - 25 Jul, 2018 - Comments: 0

Stephen Crosher, CEO of Moortec, sat down with Semiconductor Engineering to discuss on-chip monitoring and its impact on power, security and reliability, including predictive maintenance. What follows are excerpts of that conversation. SE: What new problems are you seeing in design? Crosher: There are challenges emerging for companies working on advanced nodes, including scaling and trans... » read more

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