Week In Review: Design, Low Power

New speculative execution vulnerability; Arm’s roadmap; DTCO at 3nm; RISC-V IP.

popularity

Intel disclosed a speculative execution side-channel attack method called L1 Terminal Fault (L1TF). Leslie Culbertson, Intel’s executive vice president and general manager of Product Assurance and Security, writes: “This method affects select microprocessor products supporting Intel Software Guard Extensions (Intel SGX) and was first reported to us by researchers at KU Leuven University, Technion – Israel Institute of Technology, University of Michigan, University of Adelaide and Data61. Further research by our security team identified two related applications of L1TF with the potential to impact other microprocessors, operating systems and virtualization software.” The researchers who discovered the vulnerability refer to it as Foreshadow.

All three methods target access to the L1 data cache. Microcode updates released earlier this year provide a way for system software to clear the shared cache. Intel stated that there have been no reports of the methods being used in real-world exploits and says the risk to non-virtualized updated systems is low, with mitigations creating no meaningful performance impact on test systems. More information is available through Intel’s white paper on the vulnerability. The threat of speculative execution attacks came to the fore early this year with the disclosure of the Meltdown and Spectre vulnerabilities, which affected a wide range of processors.

Tools & IP
Arm unveiled its Client CPU roadmap through 2020, including forward-looking performance estimates. Following up the Cortex-A76, released earlier this year, will be a CPU codenamed ‘Deimos.’ Expected this year, ‘Deimos’ will be optimized for 7nm and provide 15% improved compute performance. In 2019, the CPU codenamed ‘Hercules’ will become available. Optimized for 5nm and 7nm, ‘Hercules’ should improve power and area efficiency by 10%. Both are based on Arm’s DynamIQ architecture that allows clustering of multiple cores. A major Arm goal over the next five years is to break into the Windows laptop and Chromebook markets. Ian Smythe, senior director of marketing programs at Arm, said the chips are aimed at 5G, always-connected devices, where power is the primary consideration. “In laptops, 5 watts is straightforward, but in handsets we can provide high performance in 2.5 watts. So you get performance at different power points.”

Synopsys and IBM are teaming up on design technology co-optimization (DTCO) for pathfinding of new semiconductor process technologies at 3nm and below. The companies will work on DTCO to optimize transistor- and cell-level design, new transistor architectures, variation-aware models for SPICE simulation, parasitic extraction (PEX), library characterization, and static timing analysis, as well as gathering gate-level design metrics to refine the models, library architecture, and design flows to maximize PPAC benefits.

Bluespec debuted its first open-source RISC-V processor IP, a 3-stage RV32IM processor targeted at IoT applications. The IP is available as a royalty-free synthesizable Verilog core that can be integrated and deployed into an ASIC or FPGA. Bluespec also provides tools for the customization and verification of RISC-V cores. The company says configurations will be continually added to provide the full spectrum of embedded controller features.

Arasan Chip Systems launched NAND Flash Controller PHY and I/O Pad IP for 12nm SoC designs compliant to the latest ONFI 4.1 Specifications. The PHY IP supports 1.2v and 1.8v out of the box, with 2.5v and 3.3v available on request. The ONFI NAND PHY and I/O Pad IP can also be integrated with customers’ proprietary NAND Flash Controllers through a standard DDR DFE Interface.

Faraday Technology uncorked a USB 2.0 OTG PHY on UMC 40nm. The IP, which the company claims is the smallest in its class, comes with both I²C and APB interfaces for register setting. A PHY daughter board for system-level FPGA development and verification is available. The USB IP is targeted at consumer applications, such as MFP, DSC, USB portable devices, IoT, wearables, and MCUs. The IP is currently in validation phase on UMC 28nm process nodes, which will be available later this year.

Deals
Global Unichip Corporation (GUC) adopted Cadence’s Palladium Z1 emulation platform, along with Cadence’s Xcelium simulator, VIP, and formal tools, for its SoC designs. GUC cited more predictable turnaround times for full-chip emulation model builds , which enabled quick debugging.

All legal requirements have been met for the ESD Alliance to become a SEMI Strategic Association Partner, according to the organization. Integration is underway and is expected to be complete by the end of the year. The ESD Alliance will retain its own governance and its focus on the semiconductor design ecosystem.

IC Insights argues that the era of semiconductor mega-mergers may be over given growing regulatory attention to chipmaker acquisitions and the failure of Qualcomm’s $44 billion bid for NXP. “It is becoming less likely that semiconductor acquisitions over $40 billion can be completed or even attempted in the current geopolitical environment and brewing battles over global trade,” says the market research firm.

Events
Hot Chips: August 19-21 in Cupertino, CA. The symposium for high-performance chips will feature a number of sessions on machine learning architectures as well as discussions of hardware security methods, blockchain, and acceleration.

Crossing the Chasm: Building a Startup to a Successful Exit: Sept. 13, 6 p.m. – 9 p.m., at SEMI in Milpitas, CA. Jim Hogan of Vista Ventures and Amit Gupta, co-founder of Solido Design Automation, will discuss the experience of growing Solido from an EDA startup through its acquisition by Mentor, a Siemens Business, in 2017.

Electronic Design Process Symposium (EDPS): Sept. 13-14 at SEMI in Milpitas, CA. The meeting will discuss design methodologies, design flows and CAD tool needs. Focus areas include machine learning, smart manufacturing, reliability, and cybersecurity.

Arm TechCon: Oct. 16-18 in San Jose, CA. The Arm-centric conference and expo will feature keynotes by senior Arm executives as well as best-practices for implementing Arm IP in a range of designs, including IoT and automotive. The company has also teased that an expanded roadmap for future products will be released at the show.



Leave a Reply