tag: IP

IP Issues At 10/7nm
By Ranjit Adhikary - 23 Apr, 2018 - Comments: 0

For years chip makers have been demanding more options to assist them in getting silicon to market faster. As of 2018, there are now so many possibilities for chip makers that engineering teams of all types are having trouble wading through all the possibilities. To make matters worse, many of today’s choices now come with unexpected and often unwanted caveats. At the most advanced nodes... » read more

Tech Talk: Analog Simplified
By Ed Sperling - 16 Apr, 2018 - Comments: 0

Benjamin Prautsch, Fraunhofer EAS' group manager for advanced mixed-signal automation, talks about how to simplify and speed up analog IP development, its role in IoT and IIoT/Industry 4.0, and why this is becoming so important for advanced packaging and advanced process nodes. https://youtu.be/6ISL1A7Wy_I » read more

What Happened To UPF?
By Brian Bailey - 16 Apr, 2018 - Comments: 1

Two years ago there was a lot of excitement, both within the industry and the standards communities, about rapid advancements that were being made around low-power design, languages and methodologies. Since then, everything has gone quiet. What happened? At the time, it was reported that the [gettech id="31043" comment="IEEE 1801"] committee was the largest active committee within the IEEE. ... » read more

Get Ready For Integrated Silicon Photonics
By Brian Bailey - 12 Apr, 2018 - Comments: 1

Long-haul communications and data centers are huge buyers of photonics components, and that is leading to rapid advances in the technology and opening new markets and opportunities. The industry has to adapt to meet the demands being placed on it and solve the bottlenecks in the design, development and fabrication of integrated silicon photonics. "Look at the networking bandwidth used across... » read more

Tiling Is Critical For eFPGA Users: ArrayLinx Delivers
By Flex Logix - 04 Apr, 2018 - Comments: 0

FPGA chips come in multiple sizes — modular blocks of programmable logic, DSP MACs and RAM are intermixed in different sizes and ratios then stitched together with top-level interconnect, clocking, etc and surrounded by a ring of I/Os like GPIO, SerDes, USB, etc. There is extensive engineering and top-level physical design for each distinct FPGA array and chip. eFPGA is different: Custome... » read more

Tech Talk: Automotive Design
By Ann Mutschler - 22 Mar, 2018 - Comments: 0

NetSpeed Systems CEO Sundari Mitra talks about how to speed up the design of automotive chips. https://youtu.be/cus4fStDa5c » read more

The Bumpy Road To 5G
By Ed Sperling - 21 Mar, 2018 - Comments: 1

5G is coming, but not everywhere, not all at once, and not the fastest version of this technology right away. In fact, the probable scenario is that 5G will be rolled out first in densely populated urban areas, starting in 2020 or 2021, with increasingly widespread adoption over the next decade after that. But 5G is unlikely to ever completely replace 4G LTE, just as a smart phone today roll... » read more

The Week in Review: IoT
By Jeff Dorsch - 09 Mar, 2018 - Comments: 0

Finance Toronto-based Ecobee, which markets smart thermostats, raised $61 million in its Series C funding, bringing the total funding for the 11-year-old company to $146 million. Energy Impact Partners led the new round and was joined by Amazon’s Alexa Fund, Relay Ventures, and Thomvest. Ecobee counts Nest Labs, the Google subsidiary, as its chief rival. ThoughtWire, also headquartered in... » read more

Why All Nodes Won’t Work
By Ed Sperling - 08 Mar, 2018 - Comments: 4

A flood of new nodes, half-nodes and every number in between is creating confusion among chipmakers. While most say it's good to have choices, it's not clear which or how many of those choices are actually good. At issue is which [getkc id="43" kc_name="IP"] will be available for those nodes, how that IP will differ from other nodes in terms of power, performance, area and sensitivity to a v... » read more

IP And Power
By Brian Bailey - 08 Mar, 2018 - Comments: 0

[getkc id="108" kc_name="Power"] is quickly becoming a major differentiator for products, regardless of whether they are connected to a wall outlet or dependent on a battery. At the same time, increasing amounts of a chips content comes from third-party [getkc id="43" kc_name="IP"]. So how do system designers ensure that the complete system has an optimal power profile, and what can they do to ... » read more

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