tag: IP

The Battle To Embed The FPGA
By Brian Bailey - 31 Oct, 2016 - Comments: 1

There have been many attempts to embed an [gettech id="31071" comment="FPGA"] into chips in the past, but the market has failed to materialize—or the solutions have failed to inspire. An early example was [getentity id="22924" comment="Triscend"], founded in 1997 and acquired by [getentity id="22839" e_name="Xilinx"] in 2004. It integrated a CPU—which varied from an [getentity id="22186" co... » read more

Find The Best IP For You
By eSilicon - 26 Oct, 2016 - Comments: 0

It can be quite challenging and time consuming to find the right semiconductor IP for your project. You’ve got to find IP that does not consume too much power, meets your performance target, has the lowest leakage when your product goes on standby, and last but not least, IP that occupies the least amount of expensive real estate on your chip. How can you accomplish such a task without having... » read more

IP Market: CPU Still The Largest But Security Leads In Growth
By Rich Wawrzyniak - 24 Oct, 2016 - Comments: 0

The 3rd Party Semiconductor Intellectual Property (SIP) market has seen great innovation in the products it offers to System-on-a-Chip (SoC) designers over the last ten years. If any market segment in the semiconductor industry typifies the intense evolutionary pressures that the entire electronics market has undergone, it is the 3rd Party SIP market. Most of these evolutionary forces are dr... » read more

#54DAC: A New Beginning
By Michael MacNamara - 17 Oct, 2016 - Comments: 0

I’ve been attending DAC as an exhibitor since 1992, and serving on the executive committee since 2012. I am thrilled to serve as General Chair for the 54th iteration of this grand conference. (And no it’s not too early to think about DAC. The call for contributions is open now.) Through the years I have seen some big industry changes, most driven by the increasingly powerful tools and autom... » read more

Early Power Modeling Using SystemC And TSMC System-PPA
By Kurt Shuler - 10 Oct, 2016 - Comments: 0

Power consumption is often more important than performance in today’s SoC designs because of battery size and power dissipation limitations. The dilemma is that the most leverage available to optimize power consumption is at the architectural design stage, but there often is not enough information available early enough to make accurate power decisions. On the performance side, SystemC mod... » read more

What Can Go Wrong In Automotive
By Ed Sperling - 06 Oct, 2016 - Comments: 1

Semiconductor Engineering sat down to discuss automotive engineering with Jinesh Jain, supervisor for advanced architectures in Ford’s Research and Innovation Center in Palo Alto; Raed Shatara, market development for automotive infotainment at [getentity id="22331" comment="STMicroelectronics"]; Joe Hupcey, verification product technologist at [getentity id="22017" e_name="Mentor Graphics"]; ... » read more

EDA, IP Sales Up
By Ed Sperling - 29 Sep, 2016 - Comments: 0

EDA and IP sales increased 5.6% in Q2 to $2.013 billion, up from $1.907 billion in the same period in 2015, according to the most recent Electronic System Design Alliance numbers. Asia/Pacific revenue increased 10.9% to $608.1 million; Japan increased 15.7% to $211.4 million. The Americas increased 4.4% to $908.4 million. The only region that showed a decline was Europe, the Middle East ... » read more

Designers: Take Control Of Your Chip
By Mike Gianfagna - 29 Sep, 2016 - Comments: 0

This is a familiar story for us – maybe it is for you, too. From time to time, a customer contacts us and says they have a design in mind, but they just can’t fit in the package, or meet the power budget, or meet timing. Fifty percent or more of the area for many of the chips we see is composed of memory. So we start there. After a Pareto analysis of the memory sub-system, we typically find... » read more

How High-Level Synthesis Was Used To Develop An Image-Processing IP Design From C++ Source Code
By Cadence - 28 Sep, 2016 - Comments: 0

Imagine working long and hard on a design, only to learn that you need to add new (and more complex) functionality a few months before your targeted tapeout. How can you deliver the performance and capabilities expected in the same timeframe? For Bosch, high-level synthesis (HLS) provided the solution. In this paper, we will discuss how HLS technology enabled the team to meet an aggressive sche... » read more

Plugging Holes In Machine Learning
By Ed Sperling - 19 Sep, 2016 - Comments: 0

The number of companies using machine learning is accelerating, but so far there are no tools to validate, verify and debug these systems. That presents a problem for the chipmakers and systems companies that increasingly rely on machine learning to optimize their technology because, at least for now, it creates the potential for errors that are extremely difficult to trace and fix. At the s... » read more

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