tag: IP

IP Design Essentials For Power Integrity
By Annapoorna Krishnaswamy - 06 Nov, 2014 - Comments: 0

Smart connectivity is the new mantra of today – the ability to connect to anything, anywhere and at any time. With such technology enablement, low power is not a choice but an expectation. Whether it is a connected device, or a system that is part of the infrastructure, they are driven to integrate various functionality such as high speed computing, high-speed memory, memory interfaces, radio... » read more

Automated Assertion-Based Verification Methodologies For IP And SoC Development
By Atrenta - 05 Nov, 2014 - Comments: 0

The rapid growth in complexity and size of modern System on Chip devices (SoCs), along with the expense of developing these ICs, has driven the need for design reusability. Today, SoC designs are typically built as a collection of individual IP (Intellectual Property) blocks stitched together with glue logic. These IP can be sourced from multiple design teams, including many 3rd-party teams. So... » read more

A Method To Quickly Assess The Analog Front-End Performance In Communication SoCs
By Synopsys - 05 Nov, 2014 - Comments: 0

This white paper outlines a simplified method to determine if the electrical characteristics of any given AFE are adequate for the targeted application such as broadband signal transceivers in the context of wireless or wireline connectivity, cellular communications and digital TV and radio broadcast. Additionally, it illustrates a tool to explore tradeoffs between relative performance and oper... » read more

The Week In Review: Design
By Ed Sperling - 31 Oct, 2014 - Comments: 0

Tools Mentor Graphics rolled out an extension to its PCB design platform that allows for synchronization of processes across multi-board systems. The new tool captures logic and system definitions for boards, cables, backplanes, cable assemblies, sensors and actuators. Cadence introduced a dynamic characterization solution for mixed signal blocks such as PLLs, data converters, high-speed tr... » read more

Memory Directions Uncertain
By Brian Bailey - 28 Oct, 2014 - Comments: 1

Semiconductor Engineering sat down with a panel of experts to find out what is happening in world of memories. Taking part in the discussion are [getperson id="11073" comment="Charlie Cheng"], chief executive officer at [getentity id="22135" e_name="Kilopass Technology"]; Navraj Nandra, senior director of marketing for Analog/Mixed signal IP, embedded memories and logic libraries at [getentity ... » read more

Tech Talk: IP Integration Part 2
By Ed Sperling - 27 Oct, 2014 - Comments: 0

Sonics CTO Drew Wingard talks about the challenges of integrating IP into SoCs in this second of two parts. [youtube vid=ipQkPjJMcgY] » read more

Are Models Holding Back New Methodologies
By Brian Bailey - 23 Oct, 2014 - Comments: 0

Semiconductor Engineering sat down to discuss the state of the industry for [getkc id="101" kc_name="modeling"] at abstractions above [getkc id="49" kc_name="RTL"], a factor which has delayed adoption of [getkc id="104" kn_name="virtual prototypes"] and the proliferation of system-level design and hardware/software codesign. Taking part in the discussion were Frank Schirmeister, group director,... » read more

Tech Talk: SW vs. HW
By Ed Sperling - 21 Oct, 2014 - Comments: 0

Arteris CTO Craig Forest talks about what gets done in hardware, what gets done in software, and where the two worlds meet and sometimes collide. [youtube vid=-EbUTZL0uz8] » read more

Securing The IoT
By Ed Sperling - 20 Oct, 2014 - Comments: 1

Semiconductor Engineering sat down to discuss whether the [getkc id="76" comment="Internet of Things"] will be secure enough, or whether it will create new security issues, with Sami Nassar, general manager of [getentity id="22499" comment="NXP Semiconductor"]; Oleg Logvinov, director for special assignments at [getentity id="22331" comment="STMicroelectronics"]; and Lawrence Loh, application e... » read more

Week 19: Ready. Steady. Go!
By Anne Cirkel - 17 Oct, 2014 - Comments: 2

The window for submitting to the IP and designer tracks opens on Oct. 23. It’s time to get ready and check with your management if you can present your work at DAC. You can find the submission details and a link to last year’s content here. You can even browse presentation examples from past designer tracks. If you are an EDA vendor, the designer track is a good opportunity for your use... » read more

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