Surprises Abound As Subsystem IP Gains Prominence

By The SE Staff - 28 Feb, 2013 - Comments: 0

What’s new in the world of subsystem intellectual property? To find out, System-Level Design sat down with Richard Wawrzyniak, senior market analyst for ASICs and SoCs at Semico Research Corp. What follow are excerpts of that conversation. SLD: You mentioned that the cost of semiconductor intellectual property (IP) at 20nm and below is increasing. Why is that? Wawrzyniak: The reason is c... » read more

Advanced SoC Interconnect IP

By Kurt Shuler - 28 Feb, 2013 - Comments: 0

By Kurt Shuler I am thoroughly enjoying 2013. That’s because there seems to be a lot more reason for optimism this year than last year. But before we let go of 2012, it’s important to reflect on the past year and see what it can teach us so we can make better business decisions moving forward. The one lesson learned is that flexibility for SoC designs is increasingly more important. In ... » read more

Raising The Stakes For IP

By Ed Sperling - 14 Feb, 2013 - Comments: 0

By Ed Sperling As the amount of IP in an SoC increases, so do the number of players who want to strengthen their position in this market. The big acquisitions that began several years ago over time have proved to be just opening salvos—something that was impossible to predict when this shift began. Synopsys’ purchase of Virage Logic and Cadence’s purchase of Denali, both of which occu... » read more

Proving IP

By Ed Sperling - 14 Feb, 2013 - Comments: 0

As the amount of commercially available IP in a design increases, so does the level of confusion. Unlike those giant yellow stickers you get with a major appliance that tell you how much energy you’re likely to use over the course of a year and the projected cost range, there’s no such information available for semiconductor IP. In fact, there’s even resistance to provide that kind of ... » read more

The Integrated IP Subsystem: A Converging SoC Solution

By Various Writers - 31 Jan, 2013 - Comments: 0

The consumer device market is witnessing incredible market space convergence between mobile handheld, automotive, and home electronics. IP vendors, engineers, and system design engineers face a multitude of challenges when designing and developing ICs, systems, or subsystems for the next great portable device. The next cell phone for instance, will not only be a multimedia player, but also a de... » read more

What’s Ahead For System-Level Design

By Ed Sperling - 19 Dec, 2012 - Comments: 0

By Ann Steffora Mutschler Architecting an SoC today is incredibly difficult. When you add in the number of available transistors, the manufacturing effects of smaller nodes, IP and software that must be integrated, among other things, the challenges just keep mounting. Depending on what market segment the SoC will be designed into has a huge impact, as well. “It is impossible to ove... » read more

TLM-Driven Design And Verification—Time For A Methodology Shift

By Various Writers - 19 Dec, 2012 - Comments: 0

While today’s RTL design and verification flows are a step up from the gate-level flows of two decades ago, RTL flows are straining to meet the demands of most product teams. When designs are sourced and verified at the register transfer level (RTL), IP reuse is difficult, functional verification is lengthy and cumbersome, and architectural decisions cannot be confirmed prior to RTL verificat... » read more

12 Design Techniques For Successful Integration Of Data Converter IP Into An SoC

By Various Writers - 19 Dec, 2012 - Comments: 0

To deliver the demanding performance and faster operation of today’s systems—from communication interfaces to high-image-quality video and multimedia systems—consumer applications employ digital signal processing extensively. Data converters form the interface between the real-world analog signals and the digital domain. They are, therefore, an essential element of the complete signal pro... » read more

Experts At The Table: SoC Verification

By Ed Sperling - 14 Dec, 2012 - Comments: 0

By Ed Sperling System-Level Design sat down to discuss the challenges of verification with Frank Schirrmeister, group director for product marketing of the System Development Suite at Cadence; Charles Janac, chairman and CEO of Arteris, Venkat Iyer, CTO of Uniquify; and Adnan Hamid, CEO of Breker Verification Systems. What follows are excerpts of that discussion. SLD: How important is it t... » read more

Experts At The Table: SoC Verification

By Ed Sperling - 29 Nov, 2012 - Comments: 0

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tag: IP

Surprises Abound As Subsystem IP Gains Prominence

Advanced SoC Interconnect IP

Raising The Stakes For IP

Proving IP

The Integrated IP Subsystem: A Converging SoC Solution

What’s Ahead For System-Level Design

TLM-Driven Design And Verification—Time For A Methodology Shift

12 Design Techniques For Successful Integration Of Data Converter IP Into An SoC

Experts At The Table: SoC Verification

Experts At The Table: SoC Verification