tag: ISO 26262

Growing Complexity Adds To Auto IC Safety Challenges
By Ann Mutschler - 05 Nov, 2020 - Comments: 0

The automotive industry is working to streamline, automate and tame verification of automotive electronic control units, SoCs and other chips used in vehicles, many of which are becoming so complex and intertwined that progress is getting bogged down. Modern cars may have up to 100 ECUs, which control such vehicle functions as engine, powertrain, transmission, brakes, suspension, entertainme... » read more

HW Security Better, But Attack Surface Is Growing
By Ed Sperling - 08 Oct, 2020 - Comments: 0

Semiconductor Engineering sat down to discuss security on chips with Vic Kulkarni, vice president and chief strategist at Ansys; Jason Oberg, CTO and co-founder of Tortuga Logic; Pamela Norton, CEO and founder of Borsetta; Ron Perez, fellow and technical lead for security architecture at Intel; and Tim Whitfield, vice president of strategy at Arm. What follows are excerpts of that conversation,... » read more

RISC-V: What’s Missing And Who’s Competing
By Ed Sperling - 23 Sep, 2020 - Comments: 0

Part 2: Semiconductor Engineering sat down to discuss the business and technology landscape for RISC-V with Zdenek Prikryl, CTO of Codasip; Helena Handschuh, a Rambus Security Technologies fellow; Louie De Luna, director of marketing at Aldec; Shubhodeep Roy Choudhury, CEO of Valtrix Systems; and Bipul Talukdar, North America director of applications engineering at SmartDV. What follows are exc... » read more

Formal Verification Becoming Critical To Auto Security, Safety
By Ann Mutschler - 09 Sep, 2020 - Comments: 0

Formal verification is poised to take on an increasingly significant role in automotive security, building upon its already widespread use in safety-critical applications. Formal has been essential component of automotive semiconductor verification for some time. Even before the advent of ADAS and semi-autonomous vehicles — and functional safety specifications like ISO 26262 and cybersecur... » read more

Using Critical Area To Boost Automotive IC Test Quality
By Ron Press - 03 Sep, 2020 - Comments: 0

To compete in the fast-growing market for automotive ICs, semiconductor companies need to address new challenges across the entire design flow. To meet the ISO 26262 goal of zero defective parts per million (DPPM), DFT engineers have embraced new test pattern types, including cell-aware, interconnect, and inter-cell bridge (cell neighborhood). But the traditional methods of choosing the types o... » read more

Monitoring Chips After Manufacturing
By Brian Bailey - 19 Aug, 2020 - Comments: 2

New regulations and variability of advanced process nodes are forcing chip designers to insert additional capabilities in silicon to help with comprehension, debug, analytics, safety, security, and design optimization. The impact of this will be far-reaching as the industry discusses what capabilities can be shared between these divergent tasks, the amount of silicon area to dedicate to it, ... » read more

Auto Chip Reliability Opens Door To Other Industries
By Susan Rambo - 11 Aug, 2020 - Comments: 1

Digital chips in the semiconductor industry evolve from each other. Ideas flow into each other over the years, with occasional big leaps in evolution. The term ‘evolution’ fits because one chip evolves to perfectly optimized for one industry niche. But what happens when one industry’s chip becomes a useful for other industries because it is more cost-effective than what is being used i... » read more

Accellera Tackles Functional Safety
By Paul McLellan - 06 Aug, 2020 - Comments: 0

During DAC, Accellera had a workshop about functional safety. In case you don't know, Accellera has a relatively new working group (WG) on Functional Safety. The chair is Cadence's Alessandra Nardi, who coincidentally also received the Marie Pistilli Award for Women in EDA during DAC (you can read more about that in my post Alessandra Nardi Receives Marie Pistilli Award for Women in EDA). But ... » read more

CodaCache: Helping to Break the Memory Wall
By Arteris - 04 Aug, 2020 - Comments: 0

As artificial intelligence (AI) and autonomous vehicle systems have grown in complexity, system performance needs have begun to conflict with latency and power consumption requirements. This dilemma is forcing semiconductor engineers to re-architect their system-on-chip (SoC) designs to provide more scalable levels of performance, flexibility, efficiency, and integration. From the edge to data ... » read more

Creating Better Models For Software And Hardware Verification
By Ed Sperling - 04 Aug, 2020 - Comments: 1

Semiconductor Engineering sat down to discuss what's ahead for verification with Daniel Schostak, Arm fellow and verification architect; Ty Garibay, vice president of hardware engineering at Mythic; Balachandran Rajendran, CTO at Dell EMC; Saad Godil, director of applied deep learning research at Nvidia; Nasr Ullah, senior director of performance architecture at SiFive. What follows are excerpt... » read more

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