tag: JEDEC

Improving Reliability For GaN And SiC
By Mark LaPedus - 18 Jun, 2020 - Comments: 2

Suppliers of gallium nitride (GaN) and silicon carbide (SiC) power devices are rolling out the next wave of products with some new and impressive specs. But before these devices are incorporated in systems, they must prove to be reliable. As with previous products, suppliers are quick to point out that the new devices are reliable, although there are some issues that can occasionally surface... » read more

Essential DDR5 Features Designers Must Know
By Vadhiraj Sankaranarayanan - 11 Jun, 2020 - Comments: 2

JEDEC has defined and developed three DDR standards – standard DDR, mobile DDR, and graphic DDR – to help designers meet their memory requirements. DDR5 will support a higher data rate (up to 6400 Mb/s) at a lower I/O Voltage (1.1V) and a higher density (based on 16Gb DRAM dies) than DDR4. DDR5 DRAMs and dual-inline memory modules (DIMMs) are expected to hit the market in 2020. This article... » read more

ESD Requirements Are Changing
By Bryon Moyer - 11 Jun, 2020 - Comments: 1

Standards for specifying a chip’s ability to withstand electrostatic discharge (ESD) are changing – in some cases, getting tougher, and in others, easing up. ESD protection has been on a path from a one-size-fits-all approach to one where a signal’s usage helps to determine what kind of protection it should get. Protecting chips from ESD damage has been a longstanding part of IC design... » read more

The Good And Bad Of Chiplets
By Mark LaPedus - 27 May, 2020 - Comments: 1

The chiplet model continues to gain traction in the market, but there are still some challenges to enable broader support for the technology. AMD, Intel, TSMC, Marvell and a few others have developed or demonstrated devices using chiplets, which is an alternative way to develop an advanced design. Beyond that, however, the adoption of chiplets is limited in the industry due to ecosystem issu... » read more

DDR PHY Training
By Ed Sperling - 21 Apr, 2020 - Comments: 0

Brett Murdock, senior product marketing manager at Synopsys, explains how to train the DRAM physical layer using firmware, why that is so important for flexibility, and what kinds of issues engineers encounter when using this approach. » read more

HBM Issues In AI Systems
By Brian Bailey - 16 Mar, 2020 - Comments: 0

All systems face limitations, and as one limitation is removed, another is revealed that had remained hidden. It is highly likely that this game of Whac-A-Mole will play out in AI systems that employ high-bandwidth memory (HBM). Most systems are limited by memory bandwidth. Compute systems in general have maintained an increase in memory interface performance that barely matches the gains in... » read more

Enterprise-Class DRAM Reliability
By Ed Sperling - 06 Mar, 2020 - Comments: 0

Brett Murdock, product manager for memory interfaces at Synopsys, examines demand for DDR5 and DDR4 in both on-premise and cloud implementations, what features are available for which versions, how they affect performance and power, how ECC is implemented, and how the data moves throughout these systems. » read more

Week In Review: Design, Low Power
By Jesse Allen - 31 Jan, 2020 - Comments: 0

Flex Logix uncorked a new EFLX 1K eFPGA core optimized for the needs of customers on TSMC 40nm Ultra Low Power (ULP) and 40nm Low Power (LP) process technologies. It targets customers focused on low cost and power management. Using a cut-down version and the same software of the EFLX 4K, the EFLX 1K Logic core has 368 inputs and 368 outputs with 900 LUT4 equivalent logic capacity. The EFLX 1K D... » read more

Week In Review: Design, Low Power
By Jesse Allen - 17 Jan, 2020 - Comments: 0

Inphi Corporation and Synopsys finalized the acquisition of eSilicon. Synopsys acquired certain IP assets from eSilicon, including TCAMs and multi-port memory compilers, as well as its Interface IP portfolio with High-Bandwidth Interface (HBI) IP and a team of R&D engineers; it did not disclose terms of the deal. Inphi Corporation bought the rest of the company for approximately $216 millio... » read more

Pushing Memory Harder
By Brian Bailey - 14 Oct, 2019 - Comments: 4

In an optimized system, no component is waiting for another component while there is useful work to be done. Unfortunately, this is not the case with the processor/memory interface. Put simply, memory cannot keep up. Accessing memory is slow, and it can consume a significant fraction of the power budget. And the general consensus is this problem is not going away anytime soon, despite effort... » read more

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