Improved Accuracy And Robustness For Advanced DRAM With Tunable Multi-Wavelength Imaging Scatterometry Overlay Metrology

By KLA - 23 May, 2019 - Comments: 0

By Honggoo Lee, Sangjun Han, Minhyung Hong, Jieun Lee, Dongyoung Lee, Ahlin Choi and Chanha Park of SK Hynix, and Dohwa Lee, Seongjae Lee, Jungtae Lee, Jeongpyo Lee, DongSub Choi, Sanghuck Jeon, Zephyr Liu, Hao Mei, Tal Marciano, Eitan Hajaj, Lilach Saltoun, Dana Klein, Eran Amit, Anna Golotsvan, Wayne Zhou, Eitan Herzl, Roie Volkovich and John C. Robinson of KLA. Abstract Overlay process c... » read more

SiC Demand Growing Faster Than Supply

By Mark LaPedus - 23 May, 2019 - Comments: 2

The silicon carbide (SiC) industry is in the midst of a major expansion campaign, but suppliers are struggling to meet potential demand for SiC power devices and wafers in the market. In just one example of the expansion efforts, Cree plans to invest up to $1 billion to increase its SiC fab and wafer capacities. As part of the plan, Cree is developing the world’s first 200mm (8-inch) SiC f... » read more

3D NAND Race Faces Huge Tech And Cost Challenges

By Mark LaPedus - 23 May, 2019 - Comments: 8

Amid the ongoing memory downturn, 3D NAND suppliers continue to race each other to the next technology generations with several challenges and a possible shakeout ahead. Micron, Samsung, SK Hynix and the Toshiba-Western Digital duo are developing 3D NAND products at the next nodes on the roadmap, but the status of two others, Intel and China’s Yangtze Memory Technologies Co. (YMTC), is les... » read more

Week In Review: Manufacturing, Test

By Mark LaPedus - 10 May, 2019 - Comments: 0

Trade More trade news: "The Trump administration is hiking duties on $200 billion worth of Chinese products to 25% from 10%," according to CNBC. The following is attributed to Gary Shapiro, president and CEO of the Consumer Technology Association (CTA), in response to President Trump’s plan to increase tariffs on $200 billion worth of Chinese imports to 25%: “The president is seeking a bet... » read more

Gaps Emerge In Automotive Test

By Ed Sperling - 07 May, 2019 - Comments: 1

Demands by automakers for zero defects over 18 years are colliding with real-world limitations of testing complex circuitry and interactions, and they are exposing a fundamental disconnect between mechanical and electronic expectations that could be very expensive to fix. This is especially apparent at leading-edge nodes, where much of the logic is being developed for AI systems and image se... » read more

Controlling IC Manufacturing Processes For Yield

By Ed Sperling - 24 Apr, 2019 - Comments: 0

Equipment and tools vendors are starting to focus on data as a means of improving yield, adding more sensors and analysis capabilities into the manufacturing flow to circumvent problems in real time. How much this will impact the cost of developing complex chips at leading-edge nodes, and in 2.5D and 3D-IC packages, remains to be seen. But the race to both generate data during manufacturing ... » read more

Electric Cars Gain Traction, But Challenges Remain

By Mark LaPedus - 22 Apr, 2019 - Comments: 4

Battery-powered electric vehicles are expected to reach a milestone in terms of shipments in 2019, but the technology faces several significant hurdles to gain wider adoption in the market. Limited driving range, high costs, battery issues, and a spotty charging infrastructure are the main challenges for battery electric vehicles (BEVs). In addition, there are issues with various power semic... » read more

Lithography Options For Next-Gen Devices

By Mark LaPedus - 18 Apr, 2019 - Comments: 2

Chipmakers are ramping up extreme ultraviolet (EUV) lithography for advanced logic at 7nm and/or 5nm, but EUV isn’t the only lithographic option on the table. For some time, the industry has been working on an assortment of other next-generation lithography technologies, including a new version of EUV. Each technology is different and aimed at different applications. Some are here today, w... » read more

Inspecting IC Packages Using Die Sorters

By Mark LaPedus - 18 Apr, 2019 - Comments: 0

The shift toward more complex IC packages requires more advanced inspection systems in the production flow to capture unwanted defects in products. This includes traditional optical inspection tools in the in-line production flow, but it also now requires new die sorting equipment with advanced inspection capabilities. Die sorters are not the kind of equipment that typically attracts attenti... » read more

Fast Local Registration Measurements For Efficient E-beam Writer Qualification And Correction

By KLA - 09 Apr, 2019 - Comments: 0

By Klaus-Dieter Roeth, Hendrik Steigerwald, Runyuan Han, Oliver Ache, Frank Laske (KLA-Tencor MIE GmbH, Germany) Abstract Mask data are presented which demonstrate local registration errors that can be correlated to the writing swathes of state-of-the-art e-beam writers and multi-pass strategies, potentially leading to systematic device registration errors versus design of close to 2nm. Fur... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

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