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Inspecting IC Packages Using Die Sorters

Why this obscure tool is becoming crucial for finding cracking defects in optoelectronics, sensors and advanced nodes.

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The shift toward more complex IC packages requires more advanced inspection systems in the production flow to capture unwanted defects in products. This includes traditional optical inspection tools in the in-line production flow, but it also now requires new die sorting equipment with advanced inspection capabilities.

Die sorters are not the kind of equipment that typically attracts attention. For years, this technology has worked well enough to cruise well under the radar. But as more advanced inspection is required to find defects in optoelectronic components, select IC packages and other products, much is changing in the die sorting world.

Used in the IC-packaging manufacturing process, a die-sorting system picks up a die or package from a carrier, inspects it, and determines whether it passes or fails at high speeds. Die sorting equipment incorporates some inspection technologies, although the latest systems provide more advanced optical and infrared inspection. The new systems are more capable, but they also are more expensive, and packaging houses may need to buy more of them.

Generally, in the manufacturing flow, chips are processed on a wafer in a fab. Then, the wafer moves to a step called wafer sort, which is different from die sort. In wafer sort, an electrical test is conducted on a die while it’s still on the wafer. The goal is to weed out the bad dies before they move into the IC-packaging process.

From there, the wafer is moved to a packaging house, where it is processed and assembled into a package. At some point, the wafer or a wafer-like structure is diced into individual dies or IC packages, depending on the process.

The dicing step can cause defects as well as sidewall cracks on selected packages and other products. This doesn’t pertain to all packages, but it involves certain fan-in wafer-level packages (WLP) or chip-scale packages (CSPs), which are used to house various consumer, industrial and mobile chips.

For some fan-in packages, a die sorter with more advanced inspection capabilities, such as six-sided optical and infrared, is required. “Wafer-level packaging started 10 to 15 years ago for very simple packages. It did not require a lot of inspection,” said Pieter Vandewalle, general manager for the ICOS division at KLA. “Most die sorters have inspection capability, and some even have sidewall inspection with enough capability to be good enough for mainstream WLP. However, with higher-end wafer nodes, more cracks are generated since the material is more brittle. For these hairline and laser groove cracks, infrared inspection is the only appropriate technology. Traditional die sorters do not have this technology to capture the critical crack defects at production speed.”


Figure 1: IC packaging flow with die sort step. Source: KLA

In addition, the industry may require more die-sort inspection for other products like optoelectronics and sensors. Nonetheless, several companies sell die sorting systems with various inspection capabilities, including ASM Pacific, KLA, Manufacturing Integration Technology, Mühlbauer, V-TEK and others.

Why die sort?
Die sorting, which has been around for ages, is a key but overlooked step in the IC-packaging process. Generally, each package passes through a die sorter at one time or another. It’s one of many inspection steps throughout the packaging flow.

Packaging houses use different types of die sorters. For example, commodity packages with less rigid specs may require a die sorter with limited inspection. A high-volume package type, which is prone to sidewall cracks, will require a die sorter with advanced inspection. An optoelectronic part will require something different.

Die sort can take place in various places within the packaging flow. For example, in conventional packages, the finished wafer is diced into individual chips. The die is assembled into a package type and then tested.

In this case, the die sort process takes place after the dicing step. In WLPs, though, die sort may take place after the IC-packaging process.

In all cases, fab and electrical test data are fed into a die sorter system. The sorter removes a die from a carrier using a mechanism, inspects the die, and determines whether the part is good or bad. The good dies are placed on various mediums, such as a carrier tape, waffle pack, jedec tray or film frame. Some sorters perform these tasks at 30,000 units per hour (UPH).

Die sort with inspection is critical. “During the chip manufacturing process, defects may occur which impact the chip’s functionality,” said Gerald Steinwasser, a general manager at Mühlbauer. “Searching for these defects down the line is very cost-intensive and inefficient, especially after additional value has been added and further assembly process steps have been made. We see a need for precise inspection on all package types, as almost all are going through a dicing process for singulation. The level of inspection depends on the previous manufacturing steps used and on the material type.”

Sometimes industry standards require inspection. “Many applications require inspection due to the high value of the device or due to the critical end-use of the device,” said Matt Wilson, business development manager for the Royce line of die sorters at V-TEK. “For example, a sensor that may be used for autonomous driving requires as much inspection as possible to ensure that it will work correctly.”

Fan-in is one high-volume application that requires die sort with advanced inspection. “For fan-in WLP, there is no electrical test after dicing and packages are shipped to PCB assembly without final electrical test; therefore, inspection becomes more critical, especially for high-end packages that go in high-end mobile devices,” KLA’s Vandewalle said.

Die sort for fan-in
In WLPs, the dies are packaged while on a wafer. The resulting package is roughly the same size as the chip itself, which saves space on the board.

WLP involves two package types, fan-in and fan-out. One distinction is how the two package types incorporate the redistribution layers (RDLs). RDLs are the copper metal connection lines that electrically connect one part of the package to another.

In fan-out, the RDLs are routed inward and outward, enabling thinner packages with more I/Os. “In fan-out, you expand the available area of the package,” said John Hunt, senior director of engineering at ASE. “Mobile continues to be one main growth driver for both low-density and high-density fan-out. Automotive will start to pick up momentum, as we get fan-out qualified for grade 1 and 2. And server applications are seeing growth for the high-end market.”

In fan-in, the RDL traces are routed inwards. Used for a range of chips, fan-in packages are limited to about 200 I/Os and 0.6mm profiles.


Fig. 2: Fan-in vs. fan-out packages. Source: ASE

Generally, WLPs undergo many of the same process steps. Initially, the chips are diced at a packaging house. Using a pick-and-place system, the dies are placed on a wafer-like format. Finally, the RDLs are formed, creating a WLP.

At each step, defects may crop up in the IC package. “There are numerous defect challenges for advanced packaging applications,” said Amandine Pizzagalli, an analyst at Yole Développement. “The feature sizes of the RDLs are shrinking and thus could result in smaller voids or particles that will negatively impact the package device.”

At various stages, the IC package undergoes several defect inspection steps. In the in-line packaging flow, packaging houses use high-speed, optical-based defect inspection systems.

Once the package meets spec, it is then shipped to the final test and assembly phase. The WLP, which is still on a wafer-like format, is diced using mechanical or laser dicing techniques.

This is where a problem may occur. In more advanced fan-in packages, the die is encapsulated with a protective coating to prevent damage. Fan-out is encapsulated with a protective molding compound. In more traditional fan-in packages, though, the die isn’t encapsulated with a protective coating. The silicon on each side of the die is exposed. These fan-in packages are smaller and cheaper, but the package is prone to cracks and chips on the sidewalls during the dicing process and perhaps other steps. This cracking is more prevalent when a chip is processed at advanced process nodes.

Fan-in is where a die sorter with more advanced inspection fits in. The system will detect defects, and it inspects the sidewalls of the package looking for cracks and chips. “The main difference between fan-in and fan-out WLP is fan-in has exposed silicon sidewalls, while fan-out packages have mold to protect the dies inside. The aggressive dicing process can easily cause defects on silicon, while the mold on fan-out packages protects the die inside,” KLA’s Vandewalle said. “Advanced wafer nodes make use of dies with very fragile and brittle materials. And as a consequence, these materials are more subject to cracking and breaking during the dicing process. Some new defects are surfacing, like these dicing cracks in the laser grooving area during the dicing process, which require new types of inspection.”

These fragile materials involve low-k materials in chips. Today’s leading-edge chips consist of a transistor and interconnects. The transistor resides on the bottom of the structure and serves as a switch. The interconnects, which reside on the top of the transistor, consist of tiny copper wiring schemes that transfer electrical signals from one transistor to another.

In the copper interconnect stack, leading-edge logic chips have 9 to 12 metal layers. Each layer, which has a wiring scheme, is connected to another layer with vias.

Low-k materials are used as part of the copper interconnect structures in chips. Low-k materials insulate the copper wiring from the rest of the chip, but the problem is that they are fragile and prone to damage during the dicing step.

To locate defects as well as cracks on the sidewalls, optical inspection may or may not be good enough. Generally, it requires more advanced infrared inspection. Infrared inspection isn’t new. Invisible to the human eye, infrared wavelengths range between 760nm to 1,000nm. For years, infrared inspection has been used for thin-film measurements in chips. The drawback is that infrared inspection is slow and expensive.

Infrared is also critical for fan-in and other products. “It’s essentially capturing these dicing cracks. The laser grooving process step is very aggressive and creates these cracks. Together with that, it’s also inspecting the top and bottom for chipping defects and other defects,” KLA’s Vandewalle said.

With its recently introduced die sort/inspection system, KLA handles the infrared inspection steps at faster production speeds. This capability provides detection of invisible laser grooves and sidewall cracks for fan-in, memory and bare dies. KLA’s tool also supports six-sided optical inspection.

Mühlbauer, meanwhile, fields a system with similar capabilities. “Our latest generation of die sorters are capable of handling six-side inspection and infrared without losing much of the UPH [unit-per-hour] capacity. The systems can accommodate flip-chip and non-flip processes and a variety of die sizes,” Mühlbauer’s Steinwasser said.

Other apps
The issues are not limited to WLPs. “Opto-electronics such as VCSELs, side-emitting lasers, glass and even communication devices will sometimes emit or detect signals through a surface of the device,” V-TEK’s Wilson said. “These specialty devices require inspection of every surface to ensure that the signals are processed as efficiently as possible. Defects down to 1µm must be detected to ensure maximum performance for transmission and reception through these surfaces.”

Many of these apps don’t require infrared inspection. Die sorters with a wide spectrum of wavelengths can do the job. “Infrared can be a useful wavelength for detecting non-visual defects in silicon, but it has limitations to see through metal layers and heavily doped silicon. Compound semiconductor devices, such as GaN, GaAs or other III-V materials, are not transparent under infrared. So multi-spectral illumination sources tend to work better on these types of devices,” Wilson said.

For these and other applications, finding defects during die sort can help resolve various headaches for customers. Clearly, die sort is critical, even if it continues to fly under the radar.

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